_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<sajattack[m]> pdp7: maybe something is wrong with your formatting?
<sajattack[m]> I used gparted, it provides sensible defaults for fat16
<sajattack[m]> also make sure to properly eject the card
<pdp7> looks like i missing rootfs.cpio on this new card :)
<pdp7> darn same results, nothing after liftoff
<tpb> Title: Test SDCard boot with OrangeCrab · Issue #123 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)
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<sajattack[m]> any gotcha's with the fsm module? I don't see the fsm I made showing up in my design
<sajattack[m]> is it because I named it self.fsm instead of self.submodules.fsm?
<sajattack[m]> I think that was it
<sajattack[m]> now quartus fails to compile my design completely because it says I have multiple constant drivers
<sajattack[m]> I thought if there were multiple drivers it took the one furthest down the file
<sajattack[m]> oh is it because some of them are sync and some of them are comb?
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<sajattack[m]> inside a state machine, what is the difference between `NextValue(foo, 1)` and `foo.eq(1)`?
<gregdavill> The FSM module is a bit tricky before you know how it works.
<gregdavill> Everything inside `fsm.act` is combinational logic.
<sajattack[m]> yep
<gregdavill> `NextValue()` and `NextState()` are special and operate in synchronously
<gregdavill> *operate synchronously
<sajattack[m]> ok
<gregdavill> So in migen terms `foo.eq(1)` is a comb statement, `NextValue(foo, 1)` is a sync statement.
<sajattack[m]> yeah ok I think I should be using eq
<gregdavill> A trap I've fallen into is that `foo.eq(foo + 1)` will not work, because it creates a combinational loop.
<sajattack[m]> thanks
<sajattack[m]> mhm
<sajattack[m]> with tristates, am I correct that i is the input sensed value, o is the value to output, and oe is whether the pin is o or i?
<sajattack[m]> or rather a gate between o and i
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<_florent_> sajattack[m]: yes that's correct for the Tristate, set oe to 1 to use it as output
<tpb> Title: litex/gpio.py at master · enjoy-digital/litex · GitHub (at github.com)
<keesj> gregdavill: on your example foo.eq(foo +1) I think it should normaly work (at least it doen in VHDL) but the thing to remember is that in such case there are twoo foo's , the input foo and the output foo and that the output foo will not be updated until en the of the statment e.g. doing 10 times foo.eq(foo +1) would in the end result in foo.eq(foo +1)
<keesj> that is at least how I understand it
<keesj> gregdavill: also .. did you ever look at my orange crab drc ? https://github.com/keesj/orange_crab_drc
<tpb> Title: GitHub - keesj/orange_crab_drc: Script to perform some drc tests on the orange crab fpga board (at github.com)
<gregdavill> in migen if I type self.comb += foo.eq(foo + 1). It locks-up the simulator, rightly so. The isn't a way you can create a loop like that in combinational logic.
<gregdavill> keesj: I did! I'm already using this script, which covers all my needs: https://github.com/gregdavill/OrangeCrab/blob/master/lib/kicad-length-matching-checks/length_match.py
<tpb> Title: OrangeCrab/length_match.py at master · gregdavill/OrangeCrab · GitHub (at github.com)
<keesj> thanks . I will have a look at your script
<gregdavill> The one I'm using pulls net groups out of the KiCad project itself, so it's very easy to configure. But it runs in a separate terminal window, and it's not an Action Plugin.
<keesj> the default lenght matching was taking the full trace lenght including the terminaor resistors
<gregdavill> Yep, there are changes I made so it's now only checking distance of traces between two ICs.
<tpb> Title: orange_crab_drc/orange_crab_drc_action.py at master · keesj/orange_crab_drc · GitHub (at github.com)
<keesj> I was/am working on a ddr interposer
<keesj> anyway.. I will have a good look at your script
<gregdavill> The pad2pad_track_distance code is pretty cool, looks a bit better than mine performance wise.
<gregdavill> I ended up coding a messy tree structure based on track segments corresponding to a net, I then do a recursive search on this tree until I find a segment that connects to the target chip.
<keesj> Still.. quite slow. but .. in my search for a ddr3 layout.. I only found olimex and you doing stuff
<keesj> (in kicad)
<tpb> Title: Kicad_action_plugins/pad2pad_track_distance at master · MitjaNemec/Kicad_action_plugins · GitHub (at github.com)
<keesj> I was also thinking it might be cool to try and push things further e.g. from the migen/litex code generate a netlist
<dkozel> pdp7: Hope you enjoyed it
<dkozel> I got a bit enthusiastic and don't think I matched the explanation to the audience.
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<_florent_> dkozel: hi, about litepcie, you should see something in dmesg when loading the kernel module, that's strange.
<dkozel> Hi _florent_
<dkozel> I'm just settling down to try things again
<dkozel> Do you have any ideas why I had to add to kernel header includes to the main.c?
<_florent_> not sure, i'm going to prepare a repository with all the files, this way i will also do some checks.
<dkozel> Other than the kernel module is there anything I do to check that the gateware is appropriately loaded and running
<dkozel> PCI device id is different for my FPGA
<dkozel> 10ee:7024
<dkozel> Much better
<dkozel> [ 4564.845337] BUG: unable to handle page fault for address: ffffa3ac403fc000
<dkozel> [ 4564.845340] #PF: supervisor read access in kernel mode
<dkozel> [ 4564.845341] #PF: error_code(0x0000) - not-present page
<tpb> Title: [ 4564.845200] litepcie [Probing device] [ 4564.845215] litepcie 0000:03:00.0: - Pastebin.com (at pastebin.com)
<_florent_> dkozel: i just created https://github.com/enjoy-digital/litepcie_aller_test
<tpb> Title: GitHub - enjoy-digital/litepcie_aller_test: Test with LitePCIe and Numato Aller board. (at github.com)
<dkozel> Thanks will switch to that
<_florent_> With the current LiteX design, the device should be 10eee:7021, so i think the Numato bitstream is still loaded
<dkozel> Ok, Vivado does think it programmed the FPGA
<dkozel> Hmm, can we get a mask file from LiteX/Migen to use Vivado to verify the loaded bitstream?
<dkozel> yes, found the migen opts
<dkozel> My build environment for the kernel module is clearly different from yours, paths don't match
<_florent_> since you are probably just loading the bistream, you can only do a reset of the host computer, not a power on/power off otherwise the FPGA will reload the bitstream from SPI Flash
<_florent_> dkozel: which paths for example?
<dkozel> ah, and the host isn't reenumerating the PCIe device with the new bitstream
<dkozel> home/dkozel/src/litepcie_aller_test/software/kernel/csr.h:12:10: fatal error: hw/common.h: No such file or directory
<dkozel> 12 | #include <hw/common.h>
<dkozel> and the soc, mem, csr.h files needing to be in kernel/generated/ or the kernel/ directories
<_florent_> the bistream i prepared should already put the header at the right location: https://github.com/enjoy-digital/litepcie_aller_test/blob/master/aller.py#L152
<tpb> Title: litepcie_aller_test/aller.py at master · enjoy-digital/litepcie_aller_test · GitHub (at github.com)
<_florent_> also, here we have different header files for the CPU running in the FPGA and for the Host that will interfact with the FPGA over PCIe
<_florent_> the headers in generated directlry are for the CPU
<dkozel> Ok. I'm going to clean all directories, restart (kernel mod cannot be removed because it's in use) and rebuild. Back in 10 minutes
<_florent_> ok
<dkozel> Bitstream is building into the directory ./soc_pciesoc_aller/
<dkozel> so the generated files don't get written into the ./software directory
<dkozel> I can easily copy over files, is that correct?
<_florent_> with the aller.py target i provided, the header that are used by the kernel should automatically be generated to software/kernel
<tpb> Title: litepcie_aller_test/aller.py at master · enjoy-digital/litepcie_aller_test · GitHub (at github.com)
<dkozel> Ah. Just noticed that it does generate them twice, cool
<dkozel> the two kernel headers are still missing from main.c
<dkozel> I am on 5.6.0rc6 so maybe things have moved?
<dkozel> And the kernel module is loaded and detects the board!
<dkozel> And the user program works
<dkozel> 3.20 Gbps DMA works
<_florent_> nice!
<dkozel> Thanks!
<_florent_> so now if you want to generate a dumy stream on the DMA RX receive it on the computer, you can add this to the gateware: https://github.com/enjoy-digital/netv2/blob/master/netv2.py#L203-L209
<tpb> Title: netv2/netv2.py at master · enjoy-digital/netv2 · GitHub (at github.com)
<_florent_> and then do litepcie_test record dump.bin 0x1000 for example
<dkozel> Ok, that's useful
<dkozel> is there a CPU on the current bitstream? I think the default SoC does include one? I didn't pay attention to the build log
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<dkozel> Splended, works
<dkozel> I really like this ecosystem. Lots to learn!
<dkozel> Memspeed Writes: 253Mbps Reads: 320Mbps
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<_florent_> cool, that's the speed tested from the CPU, the actual speed with DMAs is a lot higher (probably around 10Gbps on Aller with a 100MHz sys_clk)
<dkozel> the netv has Gen2 x4 for it's PCI interface right?
<tpb> Title: netv2/netv2.py at master · enjoy-digital/netv2 · GitHub (at github.com)
<dkozel> Or not
<_florent_> i could do the change to use PCIe Gen2 X4 on the Aller, but first wanted to validate with PCIe Gen2 X1
<dkozel> Absolutely makes sense
<dkozel> I'm reading through the various wishbone-tool and other utility documentation now and trying things
<tpb> Title: platforms/aller: rename pcie to pcie_x4 (for consistency with others … · litex-hub/litex-boards@89dd00d · GitHub (at github.com)
<tpb> Title: target/software: add pcie_x4 support and use it as default. · enjoy-digital/litepcie_aller_test@993e05e · GitHub (at github.com)
<_florent_> you should now have PCIe gen2 X4 :)
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<dkozel> lol
<dkozel> too easy, can't work :P
<dkozel> litex.build.generic_platform.ConstraintError: Resource not found: pcie_x4:None
<dkozel> ah
<dkozel> walk before running. aka update both repos
<dkozel> Bitstream built but I need to finish a few things before rebooting the host :D
<dkozel> Thanks, will jump back in this evening on this
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<pdp7> anyone successfully used an SD card with LiteX? If so, what brand and model? I
<dkozel> Hmm. Not sure how I loaded that one image successfully earlier.
<dkozel> _florent_: How do you reboot/reset your computer without powering down the PCIe bus? I seem to be losing the image with `telinit 6`
<somlo> pdp7: hit-and-miss with LiteSDCard, pretty solid with SPI-mode SDCard -- 32 and 64 GB sandisk models
<pdp7> ah, so maybe I should be going to bigger cards like 32GB. I was thinking the opposite, trying to find smaller, older cards
<somlo> pdp7: I specifically got a 2GB card to test with LiteSDCard, and it didn't work :) The 64GB sandisk worked, the 32GB one did not
<somlo> they all work solidly with SPI-mode "spisdcard", been using the 32GB ones for the last week or so
<somlo> however -- I made a dos partition table, and added a 1GB fat16 partition table (with fdisk)
<somlo> spi-mode sdcard boot only works with fat16
<somlo> so most of the card is unused, and 1GB is "plenty space for everyone" :D
<somlo> disclaimer: I'm using litex with 64bit Rocket, so I'm only exercising this branch of spisdcardboot(): https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/boot.c#L522
<tpb> Title: litex/boot.c at master · enjoy-digital/litex · GitHub (at github.com)
<pdp7> somlo: does the sandisk show that it is from a particular product line? i could order one from amazon.
<pdp7> I used fdisk to make a 100MB partitition with FAT16 (used partition type 6)
<pdp7> and i then did "mkfs.vfat"
<pdp7> somlo: oh, and what commands did you use?
<tpb> Title: Imgur: The magic of the Internet (at imgur.com)
<pdp7> Thanks
<somlo> pdp7: also, https://pastebin.com/rWi6SpgU
<tpb> Title: # fdisk /dev/sdb Welcome to fdisk (util-linux 2.33.2). Changes will remain i - Pastebin.com (at pastebin.com)
<pdp7> somlo: thanks
<pdp7> somlo: the photo was of 32GB, but you said the 64GB worked?
<somlo> yeah, I'm looking for the amazon link of the 64 I ordered three weeks ago, stand by...
<pdp7> thanks
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<mithro> FFY00: Humans are bad at remembering and doing things reliably -- machines are great at that
<FFY00> sure
<FFY00> but unless you have machines writing your tests to make sure they cover every base, you shouldn't have automated releases on test passes