00:44 <btashton> I'm trying to bring up a board with LiteX that I have used before for other designs, but I am having issues defining the constraints on the sys_clk. Normally in Vivado I just do this

00:44 <btashton> "set_property PACKAGE_PIN B6 [get_ports sys_clk_p]" but I'm not sure how to generate that

00:45 <btashton> I am setting the IO like this ("clk100", 0, Subsignal("p", Pins("B6")), Subsignal("n", Pins("B5")) ),

09:34 <_florent_> btashton: hi, you can define your differential clock like this: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/kc705.py#L45-L48

09:34 <tpb> Title: litex-boards/kc705.py at master · litex-hub/litex-boards · GitHub (at github.com)

09:34 <_florent_> and do something similar to this in your design: https://hastebin.com/cakuwoyebo.m

09:34 <tpb> Title: hastebin (at hastebin.com)

09:35 <_florent_> otherwise you can also look at the kc705's CRG: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/kc705.py#L26-L41

09:35 <tpb> Title: litex-boards/kc705.py at master · litex-hub/litex-boards · GitHub (at github.com)

17:59 <btashton> _florent_: That is how I defined it, so I would expect the IBUFDS to be created properly. This is the error I see

17:59 <btashton> ERROR: [DRC UCIO-1] Unconstrained Logical Port: 2 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To

17:59 <btashton> correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the

17:59 <btashton> Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk100_n, and clk100_p.

19:24 <btashton> Getting closer. I forced the creation of a IBUFDS_GTE2 which seems to have solved the pin issue, just have a clock domain now with MMCME2_ADV

19:42 <_florent_> btashton: ah ok, for clocks pins that are on the transceiver block you indeed have to instantiate the clock buffer manually.

19:46 <btashton> I'm still doing something wrong with the pll in the CRG: IBUFDS_GT_loads_clock_region: IBUFDS_GTE2 IBUFDS_GTE2 drives MMCME2_ADV MMCME2_ADV in a different clock region

19:46 <btashton> https://hastebin.com/lokogezewo.rb

19:46 <tpb> Title: hastebin (at hastebin.com)

23:24 <pdp7> gregdavill: I'm trying master of linux on litex but get:

23:24 <pdp7> https://www.irccloud.com/pastebin/ZYpNk8Cb/

23:24 <tpb> Title: Snippet | IRCCloud (at www.irccloud.com)

23:24 <pdp7> for make.py --board=orangecrab --load

23:27 <gregdavill> the load option is trying to use the external JTAG debugger wish openocd.

23:29 <pdp7> what do you use for the load with usb?

23:30 <pdp7> just dfu ?

23:30 <pdp7> build/orangecrab/gateware/top.bit ?

23:34 <gregdavill> Yep. Master doesn't have any of the FLASH changes in there yet, so it should just try to load images off the sd_card. I've not tried that yet, it sounds like there is some more debugging required.

23:37 <pdp7> bingo

23:38 <pdp7> thanks

23:38 <pdp7> btw, what causes it to wait for me to start my terminal?

23:38 <pdp7> that is a nice feature

23:41 <pdp7> oh greg left... but yes, fyi - i still have not been able to get sd boot working