_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<rohitksingh> dkozel: hi! sorry I missed your message
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<dkozel> rohitksingh: Hi, good morning
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<dkozel> No worries at all, busy times
<_florent_> rjeschmi: sorry that's difficult to help without more information, can you provide a mimimal code or create an issue in LiteEth to better understand what you are trying to do and how the issue can be solved?
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<dkozel> Xilinx programming cable coming in on Thursday.
<rjeschmi> _florent_: thanks for your help
<tpb> Title: litex-boards/pano_logic_g2.py at pano_logic_g2 · rjeschmi/litex-boards · GitHub (at github.com)
<tpb> Title: litex-boards/pano_logic_g2.py at pano_logic_g2 · rjeschmi/litex-boards · GitHub (at github.com)
<rjeschmi> I managed to add just the phy, but adding the etherbone started throwing the errors
<rjeschmi> If it is easier I can PR it (and/or open an issue)
<_florent_> yes that could be easier to open a PR on liteeth to discuss
<rjeschmi> ok, I'm not changing anything in liteeth for this though
<rjeschmi> except that maybe the gmii phy is not well tested?
<rjeschmi> I can open an issue on that
<tpb> Title: Issues with GMII · Issue #37 · enjoy-digital/liteeth · GitHub (at github.com)
<_florent_> rjeschmi: some board/fpga can have some limitations, the actual codebase is tested with combination already encountered that's possible some changes could be needed for your design, thanks for the PR, i'll look at that
<rjeschmi> the build.log is just a capture of all the output. I can upload other files as needed
<_florent_> dkozel: ok for the programming cable, i just updated the Numato targets to be similar to the Netv2 design: https://github.com/litex-hub/litex-boards/commit/85f38876c29defdcd7971bdd4e8e6788c6c9606c
<tpb> Title: targets: update PCIe on Numato targets. · litex-hub/litex-boards@85f3887 · GitHub (at github.com)
<rjeschmi> _florent_: yeah, I understand that. This is mainly a learning exercise for me, so I'm happy to poke more into the code with a bit of guidance
<_florent_> dkozel: you should be able to use the software from https://github.com/enjoy-digital/netv2/tree/master/software (copy the generated csr.h/soc.h/mem.h to kernel and maybe just comment the SPIFLASH related accesses)
<tpb> Title: netv2/software at master · enjoy-digital/netv2 · GitHub (at github.com)
<rjeschmi> for this particular design I already experimented with pinning rst_n in order to keep the 125MHz clock (they pull the 125 clock through the phy PLL)
<_florent_> rjeschmi: can you try to comment:
<tpb> Title: litex/ise.py at master · enjoy-digital/litex · GitHub (at github.com)
<tpb> Title: litex/ise.py at master · enjoy-digital/litex · GitHub (at github.com)
<_florent_> and see if you are able to build the design?
<_florent_> it seems the automatic keep attributes are causing issues with ISE
<rjeschmi> ok sure
<_florent_> rjeschmi: can you add your .ucf to the PR? just to understand which constraint is failing
<rjeschmi> yeah for sure
<rjeschmi> I was just going to mention that
<rjeschmi> _florent_: I had to rename it to a .txt due to file type restrictions, but it is there now
<_florent_> ok thanks. I'm going to look at that. I also created https://github.com/enjoy-digital/litex/issues/438 since that's not the first time we see this
<tpb> Title: ISE: automatic "keep" attributes on constraints signals seems to cause issue in the build. · Issue #438 · enjoy-digital/litex · GitHub (at github.com)
<rjeschmi> _florent_: there is certainly something related to how the constraints are added.
<rjeschmi> using the with_etherbone helper adds the constraints to cd_eth_rx, but that doesn't seem to exist in the top.ucf (as the error points out)
<dkozel> _florent_: thanks for the updated software. I'll let you know when I have it programmed.
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<tpb> Title: phy/gmii: use a BUFG between eth_rx.clk and eth_rx.clk. · enjoy-digital/liteeth@fb47853 · GitHub (at github.com)
<rjeschmi> _florent_: thanks. I'll test it out
<rjeschmi> _florent_: In my initial testing it seems to resolve half the errors (eth_tx_clk is there), but the eth_rx_clk still seems to be missing
<rjeschmi> _florent_: I think it may be a local issue
<rjeschmi> I'll update when sure
<rjeschmi> _florent_: making significant progress, thanks
<rjeschmi> I had to add a CLOCK_DEDICATED_ROUTE = FALSE to the nets just to demote it to a warning and get it to route
<tpb> Title: HDMI2USB-litex-firmware/net.py at master · timvideos/HDMI2USB-litex-firmware · GitHub (at github.com)
<rjeschmi> like that
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<fkokosinski> _florent_ hi! I'm tinkering with litevideo (with mode=ycbcr) right now and have a problem with colors being "off" (it doesn't seem to follow any particular pattern). Have you encountered any issues with litevideo in ycbcr mode in the past? I can share photos of it if you want
<fkokosinski> in rgb mode colors seem to be okay, though
<_florent_> fkokosinski: hi, yes that could help to have photos, also not sure if you are aware but ycbcr is in 4:2:2 not 4:4:4
<fkokosinski> _florent_ yes, i'm aware of that. Output from gst's testvideosrc: https://drive.google.com/file/d/1EhJ1nZi25MRj_JzhRIX5Q4-RtxtEeqfP/view (good colors) https://drive.google.com/file/d/1dixrY66UpxUBaqL_2zpXQ0imnTx9n3fJ/view (colors being "off"). Sorry for frames not being in sync
<tpb> Title: frame_good.png - Google Drive (at drive.google.com)
<_florent_> fkokosinski: i would say cb interpreted as cr and cr as cb, it could be a 16-bit shift in the stream
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<tcal> kgugala: to continue the conversation from the meeting, regarding the zephyr/vexriscv/tflite magic wand demo: Doing "make gateware-load" works, but the tutorial in the README.md just ends there with no further instructions. On another page I found "make firmware-connect". This works to the point that I get a "litex>" BIOS prompt. Then, going back to the Antmicro blog post, I found: "The onboard FPGA chip has to be programmed with ga
<tcal> teware bitstream. After the board has been programmed, the LiteX System will boot. On a serial console you should see a Litex Bios prompt. In order to run the demo, the compiled application binary has to be uploaded to the device. The binary can be uploaded to the device using the serial connection with the litex_term tool.". I will try to figure that out, but it seems it would be useful if the REAADME.md instructions would explicitly sp
<tcal> ell out the "make firmware-connect" and "litex_term" steps.
<tcal> Ok, I may have made some progress. I found a RISC-V webpage that used litex_term.py, so by copying their method but using "top.bin" from the demo build, I may be getting somewhere. We'll see after it finishes downloading....
<tcal> I'm not sure if this is good or not:
<tcal> SDRAM now under hardware control
<tcal> --============== Boot ==================--
<tcal> Memtest OK
<tcal> Press Q or ESC to abort boot completely.
<tcal> Booting from serial...
<tcal> sL5DdSMmkekro
<tcal> [LXTERM] Received firmware download request from the device.
<tcal> [LXTERM] Uploading build/arty_tf_vexriscv.full/gateware/top.bin to 0x40000000 (2192012 bytes)...
<tcal> [LXTERM] Upload complete (3.7KB/s).
<tcal> [LXTERM] Booting the device.
<tcal> [LXTERM] Done.
<tcal> Executing booted program at 0x40000000
<tcal> --============= Liftoff! ===============--
<tcal> [then no response]
<tcal> But using this approach, I don't see a "litex>" BIOS prompt, so maybe this is all wrong.
<sajattack[m]> you're trying to execute gateware as a program
<sajattack[m]> that's not what you're supposed to do
<sajattack[m]> gateware is the hardware configuration that's supposed to be loaded into the fpga
<sajattack[m]> you flash it with your vendor's tools
<sajattack[m]> the firmware you're looking for is in another castle
<keesj> isn't it just the kernel argument that is needed? https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_term.py#L351
<tpb> Title: litex/litex_term.py at master · enjoy-digital/litex · GitHub (at github.com)
<keesj> it has been a while but I remember that you can use the term to upload a program
<tcal> Yep!
<tcal> I have been now trying "--kernel ../tensorflow/tensorflow/lite/micro/tools/make/gen/zephyr_vexriscv_x86_64/magic_wand/CMake/zephyr/zephyr.bin".
<tcal> I then get a stream of errors, probably explained because I don't have the accelerometer plugged in yet:
<tcal> Register read failed with rc=-5
<tcal> Failed to read FIFO status rc = -5
<tcal> Fetch failed
<tcal> [same thing repeated indefinitely]
<tcal> So I think I'm unstuck; I'll try again when I get the ACL module tomorrow.
<tcal> Thanks all!
<keesj> cool
<tcal> For the record, my usage was: ./litex_term.py --serial-boot --kernel ../tensorflow/tensorflow/lite/micro/tools/make/gen/zephyr_vexriscv_x86_64/magic_wand/CMake/zephyr/zephyr.bin /dev/ttyUSB1
<keesj> are you doing something with machinelearning on fpga?
<tcal> Not yet :) I just started working for Tim A (Mithro) at Google. So just getting up to speed with LiteX & Arty boards. My first real project will be getting Linux running on the 100T Arty board.
<sajattack[m]> cool, I didn't know mithro worked at google
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<mithro> 11+ years now...
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<tcal> The accelerometer arrived,
<tcal> --============= Liftoff! ===============--
<tcal> Got id: 0xe5
<tcal> *** Booting Zephyr OS build v1.7.99-24033-g52f4b7aa0f8e ***
<tcal> Got accelerometer
<tcal> But haven't been able to recognize anything.
<mithro> I actually haven't run this demo myself
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<tcal> I did get "slope" recognized. I probably just haven't figured out the right orientation to hold the board while making the motions. There's an Arduino demo (https://www.youtube.com/watch?v=Lfv3WJnYhX0) -- this is probably based on that.
<pdp7> gregdavill: i'm about to try the OrangeCrab zip from _florent_
<pdp7> needed to find an SD card I could erase first :)
<gregdavill> pdp7: Cool! I won't be able to try it for a couple of hours.
<pdp7> _florent_: I tried the SD card but nothing seems to happen
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<pdp7> I put the crab into DFU