_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<awygle> does litedram use OCD calibration for DDR2?
<_florent_> awygle: for OCD/DDR2, we are configuring it to the default settings: https://github.com/enjoy-digital/litedram/blob/master/litedram/init.py#L107-L108
<tpb> Title: litedram/init.py at master · enjoy-digital/litedram · GitHub (at github.com)
<_florent_> awygle: creating a LiteDRAM DDR2 standalone controller is easier than DDR3/DDR4 since the initialization is just a sequence of commands , so it can be done with a FSM doing Wishbone/CSR accesses
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