_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<zyp> I tried that commit from yesterday, it's finding the /5*96/10 solution, which appears to work fine in practice despite violating the 8MHz CLKI minimum
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<_florent_> zyp: thanks for the feedback, i'll also do some test with clarity to see if we should also restrict the ranges (and eventually allow user to bypass for test purpose with an option)
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