_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<peepsalot> hi, i'm just starting to learn about litex/migen and curious about how to develop new soft cpu cores. are there currently any fine grained reusable modules that are shared across architectures? i guess I'm picturing some config that defines supported opcodes, and can generate an instruction decoder, modules to define ALUs of various widths and capabilities, L1cache modules etc.
<peepsalot> i'm also a software dev by trade, and not familiar with HDL yet so this project looks great to me. i've been loath to learn Verilog directly so far as its so ugly
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<gregdavill> I'm wanting to add a clock domain crossing to ValentyUSB eptri. It currently needs to run in a 12MHz clock domain for the USB side.
<gregdavill> I want to run my SoC at 48MHz+ and trying to work out the best way/place to add cdc elements.
<gregdavill> Its interface with the SoC is entirely though CSRs.
<gregdavill> Is there an easy way to do this?
<gregdavill> I'm thinking of wrapping the CSRs and using a Async FIFO with address/data/re/we signals. I think this will satisfy the CSR bus cycle.
<gregdavill> that seems like a better plan than keeping the CSRs in the SoC and breaking out each signal through a separate cdc element to the lower speed domain.
<peepsalot> why is there a litex-boards repository which is separate from https://github.com/m-labs/migen/tree/master/migen/build/platforms shouldn't they ideally be in sync?
<tpb> Title: migen/migen/build/platforms at master · m-labs/migen · GitHub (at github.com)
<peepsalot> i saw that de10nano was added for litex, but not migen
<sajattack[m]> I added the de10nano to litex because it's what I was using
<sajattack[m]> if you want to copy it over somewhere else go right ahead
<peepsalot> oh, hi sajattack[m], i found this from atari-forums litex linux thread btw :)
<sajattack[m]> cool
<sajattack[m]> I'm not sure how a litex board definition differs from a migen one
<sajattack[m]> I've only ever used migen in the context of litex
<peepsalot> i'm sort of curious about developing other MiSTer cores using litex/migen
<sajattack[m]> It can be done, but it's probably not how I'd go about doing things
<sajattack[m]> because all the core MiSTer tooling is systemverilog, and the verilog output from litex is pretty ugly
<sajattack[m]> I'm using litex because it's the only way I could figure out how to get a functioning risc-v soc
<sajattack[m]> verilog's not so hard
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<levi> This book is a pretty straightforward intro to doing FPGA stuff with Verilog too: https://www.amazon.com/FPGA-Prototyping-Verilog-Examples-Spartan-3/dp/0470185325 The FPGA it targets is pretty outdated now, but most of it transfers pretty well to other dev boards.
<tpb> Title: GitHub - antmicro/arty-expansion-board: IO expansion board compatible with Digilent Arty A7 (at github.com)
<futarisIRCcloud> Anyone got one of these? mithro, didn't I mention the MAX3421E back in 2018?
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<futarisIRCcloud> Hi gregdavill.
<gregdavill> I guess a standard USB PHY with ULPI takes up too many signals for a single PMOD, the SPI based approach is nice.
<futarisIRCcloud> I've got some USB-C PMODs from kbeckmann ...
<futarisIRCcloud> The Arduino shield I linked to in 2018 should also work with Arty.
<mithro> gregdavill: valentyusb already has CDC stuff unless xobs deleted it?
<xobs> mithro: there's no CDC stuff in valentyusb. If you use tinyusb, you can have cdc support with eptri.
<xobs> Jamie Craig (madhacker) was working on getting it working as part of a 6502 project, however: https://github.com/jamesacraig/6502-on-fomu/blob/master/fomu_usb_cdc.py
<tpb> Title: 6502-on-fomu/fomu_usb_cdc.py at master · jamesacraig/6502-on-fomu · GitHub (at github.com)
<gregdavill> Does it? in eptri? I only saw a 'cdc' boolean, that gets passed into the debug bridge. The CSRs and FIFOs look like they always live in the 12MHz domain.
<gregdavill> I'm attempting to get CircuitPython running. Ideally I want to run it from the SDRAM. But I can't get enumeration, because I think the fetch time in SDRAM is too slow.
<gregdavill> I think xobs 'solved' this on the Fomu, by moving all time critical stuff into a blockram fro execution.
<xobs> Oh! Right, CDC. Overloaded acronym. Sorry.
<mithro> Ahh, only all the *other* interfaces than eptri have CDC
<xobs> I thought you meant cdc_acm. You mean clock domain crossing.
<xobs> Right, I wasn't sure how to get cdc working with eptri. That's a longstanding issue. dummyusb has cdc which does, in fact, work correctly.
<mithro> Yes, clock domain crossing
<mithro> Just use a FIFO with one end in sys and one end in usb_12
<mithro> epfifo has an example
<gregdavill> Okay, I'll have to take a look through the other valentyusb.cpu interfaces, thanks!
<futarisIRCcloud> CDC = Centres for Disease Control / USB Communications Device Class / Clock Domain Crossing
<futarisIRCcloud> TLA are not confusing at all.
<mithro> If you clocks are aligned, you have an even easier time
<mithro> The fact that flipflops in an FPGA have setup + hold times which (have to) meet your fast clock mean you only need to worry about metastability from clock phase
<mithro> Another option is to just use a clock-enable strobe
<gregdavill> Ohh, so the usb_12 is actually clocked at 48, but only has a CE pulse every 4th clock.
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<gregdavill> That might work well on the ECP5, since it easily meets timing. and it's trivial to setup with a `CEInserter()`
<mithro> If I recall correctly the capture frontend uses a 48MHz clock with a recovered strobe at 12MHz...
<mithro> Snap :-P
<mithro> Writing on my phone while I walk home is slow
<gregdavill> FYI, I did implement a hardware based USB Communication Device Class. Very much a work in progress, but it's a statemachine that captures the CSR registers and sits behind eptri.
<tpb> Title: valentyusb/cdc_eptri.py at hw_cdc_eptri · gregdavill/valentyusb · GitHub (at github.com)
<gregdavill> I've been using it with linux-on-litex on orangecrab/hadbadge for the UART link. Been working well.
<xobs> gregdavill: fancy!
<xobs> another option is to add a uart in litex in "crossover" mode and use `wishbone-tool -s terminal`.
<futarisIRCcloud> Fancy indeed.
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<peepsalot> i tried to follow the instructions here https://github.com/litex-hub/linux-on-litex-vexriscv but can't get the sim.py to run. the way the steps are all split up is a bit confusing. the end of prerequisites has cd into the git dir, but are any of the other steps supposed to actually be done inside that directory?
<tpb> Title: GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv (at github.com)
<peepsalot> it errors out on compiling xgmii_ethernet.c
<sajattack[m]> peepsalot if you want I can send you my de10nano build
<sajattack[m]> You'll need an ftdi cable though
<peepsalot> sajattack[m]: sure that could be helpful, though i'm also wanting to learn/setup the tools properly.
<peepsalot> by build you mean like rbf + linux image? where does the linux image go if there's no sd support? its loaded straight to sdram via serial?
<sajattack[m]> I think your issue might be a non-recursive clone, not sure
<sajattack[m]> Yes loaded straight over serial via ftdi
<peepsalot> ok, i think i have one around here somewhere, there's nothing altera specific about the connection device, right?
<sajattack[m]> no
<sajattack[m]> just plug into the arduino rx/tx and the pin next to it is grounded
<sajattack[m]> I think I have to recompile my image, I've been messing with some stuff
<sajattack[m]> it's the last 3 pins not covered by the io board
<peepsalot> i have a cp2102
<sajattack[m]> that should work
<sajattack[m]> you also need quartus to flash the rbf
<peepsalot> i forget if its 5 or 3.3v, or configurable somehow. haven't messed with it in a while
<sajattack[m]> yeah make sure it's 3.3v
<peepsalot> i have quartus 19.1 installed, tried getting 17.x setup but it wasn't working on ubuntu
<sajattack[m]> It shouldn't matter, you only need the programmer part and I think it's the same
<sajattack[m]> gimme a sec to unfuck the stuff I've been messing with
<peepsalot> yeah looks like its 3.3v data only on the cp2102. i was a little confused because the board have a breakout pin for 5v and 3.3v, but that's just passing the usb rail through
<peepsalot> sajattack[m]: did you try the simulator at all?
<sajattack[m]> no lol
<peepsalot> k, just curious
* sajattack[m] posted a file: de10nano-litex-wip.zip (5130KB) < https://matrix.org/_matrix/media/r0/download/matrix.org/VaALvSDEDXCgaIdmBazeXCqg >
<sajattack[m]> oh oops that zip is missing some stuff
<sajattack[m]> 1 sec
<sajattack[m]> oh oops I lost a bit when I git reset
<sajattack[m]> I'll give you this version anyway
* sajattack[m] posted a file: de10nano-litex-wip.zip (5136KB) < https://matrix.org/_matrix/media/r0/download/matrix.org/TbiExRIoidBywBupdltpTiRA >
<sajattack[m]> that version's not filling the whole screen
<sajattack[m]> I only laughed when you asked if I did the simulation because it's bad practice not to test things in simulation first
<peepsalot> :)
<sajattack[m]> ok, full screen version
* sajattack[m] posted a file: de10nano-litex-wip.zip (5119KB) < https://matrix.org/_matrix/media/r0/download/matrix.org/sbsaIlbKZgEUHqgyujIydxio >
<sajattack[m]> which part of simulation where you stuck on?
<sajattack[m]> * which part of simulation were you stuck on?
<peepsalot> xgmii_ethernet.c:110:8: error: variable 'ret' is used uninitialized whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized]
<peepsalot> i was just trying to call sim.py and it would automatically start building libraries or something
<sajattack[m]> yeah but what part is that? what command?
<sajattack[m]> ok
<sajattack[m]> oh it's probably because your gcc is newer than what's targeted by litex or something
<sajattack[m]> I would add -Wno-sometimes-uninitialized to CFLAGS
<peepsalot> oh, yeah, its running clang-9 :P
<peepsalot> i haven't flashed with quartus before, and evidently am too dumb to figure this out. you use the usb blaster port? what "mode" for programmer?
<sajattack[m]> jtag
<peepsalot> i guess i'm missing usb-blaster driver for linux?
<sajattack[m]> maybe
* sajattack[m] uploaded an image: 2020-02-28-040830_960x595_scrot.png (67KB) < https://matrix.org/_matrix/media/r0/download/matrix.org/yKXWBycoryEgHBxgyQHSRzFb >
<peepsalot> ok, i had to change udev rules, looks like it sees it now
<peepsalot> sajattack[m]: you use the pins corresponding to tx/rx on this image? the pin next to it isn't gnd though? or its configured that way for this specific core?
<sajattack[m]> yeah, unused pins are automatically ground
<sajattack[m]> don't forget to connect tx to rx and rx to tx because uart is dumb that way
<peepsalot> is 1e6 valid rate? i think cp2102 only does 921600
<sajattack[m]> oh
<sajattack[m]> it works on ftdi
<peepsalot> idk, i just get: [LXTERM] Starting....
<sajattack[m]> press enter at that
<sajattack[m]> and it should give you the prompt
<sajattack[m]> idk why it does that
<daveshah> 1e6 is known not to work on cp2102, afaik you have to use 500k for those parts
<sajattack[m]> ok let me compile you a slower build
<tpb> Title: KC705: Lower uart_baudrate? · Issue #91 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)
<sajattack[m]> see if that works peepsalot
<peepsalot> i also have a pl2303 i could try?
<sajattack[m]> the datasheet for that says it supports 1.2M so it might work
<peepsalot> eh, i just don't know if its putting out 5v signals or not, its capable of either depending on how its connected, but the adapter is overmolded so can't see how its wired up.
<peepsalot> pain in the butt serial connections
<sajattack[m]> just try the 500k build then
<peepsalot> hrm, weird i got litex> prompt but can't type after that
<peepsalot> using 500000 build
<sajattack[m]> speed=500000?
<peepsalot> yes
<sajattack[m]> it worked for me so idk
<peepsalot> ok 2nd time worked *shrug*
<peepsalot> re-uploaded in quartus and connected lxterm again
<peepsalot> thanks for all the help
<peepsalot> still uploading image...
<sajattack[m]> cool glad you got it
<sajattack[m]> oh btw are you using 32mb or 128mb sdram?
<peepsalot> 128, is that a problem?
<sajattack[m]> idk
<sajattack[m]> I've always used 32
<sajattack[m]> I want to know if it will work with both
<peepsalot> oh wait, lol actually i have 0 RAM on this board, i guess i should swap it over. i have this separate de10 for learning development and one i use just for mister(with 128MB), forgot about that aspect
<sajattack[m]> oops
<sajattack[m]> haha
<peepsalot> is it not feasible to integrate with the onboard ddr3?
<sajattack[m]> it's difficult because the hps interface is in the way
<sajattack[m]> litex doesn't have any knowledge of the hps
<peepsalot> ok, yeah i know it has to go through hps somehow, but i still don't really understand the details of how that works. isn't the hps over avalon bus, which litex knows about?
<sajattack[m]> tbh idk
<sajattack[m]> if you figure it out, send a pr :P
<_florent_> peepsalot, sajattack[m] : do you have a link to the MiSTer verilog/VHDL code that integrate the HPS? just to have a look at the interfaces.
<peepsalot> don't really know which cores/where its used exactly
<sajattack[m]> I'll have a look
<peepsalot> it might be a drop in intel IP
<peepsalot> ?
<sajattack[m]> this might be it? looks a bit small https://github.com/MiSTer-devel/Genesis_MiSTer/blob/master/sys/ddr_svc.sv
<tpb> Title: Genesis_MiSTer/ddr_svc.sv at master · MiSTer-devel/Genesis_MiSTer · GitHub (at github.com)
<_florent_> is there a common verilog/VHDL code that each MiSTer FPGA core reuses? or does each core create a full FPGA image?
<_florent_> sajattack[m]: thanks, i'm going to look
<sajattack[m]> the sys folder is common to each core pretty much
<tpb> Title: Genesis_MiSTer/ddram.sv at master · MiSTer-devel/Genesis_MiSTer · GitHub (at github.com)
<_florent_> sajattack[m]: the easier would probably be to create a LiteX platform with a similar pinout than the emu Module: https://github.com/MiSTer-devel/Main_MiSTer/wiki/Core-porting-notes
<tpb> Title: Core porting notes · MiSTer-devel/Main_MiSTer Wiki · GitHub (at github.com)
<_florent_> sajattack[m]: and then reuse theses interfaces to communicate with the ARM or DDR3
<_florent_> these
<sajattack[m]> yeah I was planning to stick it in the emu module eventually
<sajattack[m]> but how do I get litex to generate the right signals?
<_florent_> i can create a template for that
<sajattack[m]> ok thanks
<sajattack[m]> could you do something with litesdcard too or not ready yet?
<_florent_> to create a standalone litesdcard core?
<sajattack[m]> instead of serialboot
<sajattack[m]> that wiki might be a bit out of date, I think there are sdcard signals too
<sajattack[m]> oh actually I forgot, there's two sdcards
<sajattack[m]> one with standard sdcard signals on the io board, and one with ioctl
<tpb> Title: Genesis_MiSTer/Genesis.sv at e0b367749da88836c226c6a269e09b6aa363497b · MiSTer-devel/Genesis_MiSTer · GitHub (at github.com)
<sajattack[m]> I think this module maps between the two https://github.com/MiSTer-devel/BBCMicro_MiSTer/blob/master/sys/sd_card.v
<tpb> Title: BBCMicro_MiSTer/sd_card.v at master · MiSTer-devel/BBCMicro_MiSTer · GitHub (at github.com)
<sajattack[m]> so ideally I'd like that
<_florent_> For generating the emu core with LiteX, you could use this as a template: https://hastebin.com/jatekurefo.py
<_florent_> this will generate a core like this: https://hastebin.com/xapogesado.php
<sajattack[m]> ok, sorry, how does that fit in with litedram though?
<sajattack[m]> I can map litex to emu by hand
<_florent_> this will just allow you to create a LiteX SoC inside the EMU framework of MiSTer, you then have to reuse the interfaces already provided by the EMU framework
<sajattack[m]> sorry, my question is, how do I get litedram to give me signals for the mister interface? does it already have similar ones?
<_florent_> the interface in the EMU framework for the SDRAM is a simplified interface, so no need for LiteDRAM, it can probably be easily connected to the wishbone bus
<sajattack[m]> if I look at another core with ddr, the signals lok different
<sajattack[m]> ok
<sajattack[m]> I know very little about wishbone
<_florent_> you can find useful information about it at:
<tpb> Title: Building a Simple Wishbone Master (at zipcpu.com)
<sajattack[m]> are you saying these signals https://github.com/MiSTer-devel/Genesis_MiSTer/blob/e0b367749da88836c226c6a269e09b6aa363497b/Genesis.sv#L85 map to line 72 of your hastebin?
<tpb> Title: Genesis_MiSTer/Genesis.sv at e0b367749da88836c226c6a269e09b6aa363497b · MiSTer-devel/Genesis_MiSTer · GitHub (at github.com)
<tpb> Title: Building Formal Assumptions to Describe Wishbone Behaviour (at zipcpu.com)
<tpb> Title: litex/wishbone.py at master · enjoy-digital/litex · GitHub (at github.com)
<_florent_> line 72 of the template or generated verilog?
<sajattack[m]> generated verilog
<sajattack[m]> or line 16
<_florent_> not directly, you will need to understand the protocol used for the SDRAM interface on MiSTer, how wishbone works and create a bridge between both
<sajattack[m]> ok
<tpb> Title: litex/wishbone2csr.py at master · enjoy-digital/litex · GitHub (at github.com)
<sajattack[m]> I got some reading to do 😅
<sajattack[m]> ok I read all the things
<somlo> _florent_: it just occurred to me (after a week of doing *completely* different things) to actually ask you: what brand of microSD card have you used successfully with liteSDCard on nexys4ddr? :)
<sajattack[m]> _florent_: could you show me where litedram bridges to wishbone so I can get a better idea of what it looks like for a memory interface?
<somlo> should have asked a week ago, and ordered the *right* one, and done things in parallel, but that's usually not how it works out for me...
<somlo> sajattack[m]: I think you're looking for this block: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L981 (but _florent_ can correct me if I'm wrong)
<tpb> Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com)
<sajattack[m]> I think this is what I was looking for actually https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/wishbone.py
<tpb> Title: litedram/wishbone.py at master · enjoy-digital/litedram · GitHub (at github.com)
<somlo> oh, that's how you get litedram to expose a wishbone port; I thought you're looking for where it hooks into the litex SoC -- but yeah...
<sajattack[m]> yeah, I'll need to do both, so thanks
<sajattack[m]> would anyone have any ideas why when I change my system clock from 50MHz to 100MHz, linux fails to boot
<daveshah> Does memtest pass?
<sajattack[m]> good thought, I'll check
<daveshah> If not, the SDRAM clock phase might need changing
<sajattack[m]> ok
<sajattack[m]> it's phase shifted -10000 for 50MHz, do I just double it or something?
<daveshah> Halve it
<daveshah> I'm assuming 10000=10ns=half cycle at 50MHz
<sajattack[m]> ok
<daveshah> It might need finer tuning than that though, idk
<sajattack[m]> let's find out
<sajattack[m]> yeah, looks like it needs fine tuning
<sajattack[m]> maybe I'll find something in altera and bring it over
<sajattack[m]> the random msiter core I picked out isn't doing any phase shifting for sdram
<sajattack[m]> or maybe it's doing it within the controller rather than the pll
<Claude> this will be my weekend :) first trying to get yosis/nextpnr running on the pi . then maybe some DVI/hdmi fun https://usercontent.irccloud-cdn.com/file/JXlXbYwe/IMG_20200228_175426.jpg
<sajattack[m]> neat
<sajattack[m]> are you bitbanging jtag on the pi or something?
<Claude> Yes that's the plan , openocd on pi gpio
<Claude> Later (probably very very later..) I try myself on a migen/LiteX raspi SMI (parallel bus master peripheral) to some wishbone master
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<_florent_> somlo: the last SDCard i tested with the Nexys4DDR is a SanDisk Ultra 16GB
<_florent_> Claude: nice!
<sajattack[m]> I can't find a working phase shift for 100mhz
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<_florent_> sajattack[m]: not sure i tested sdram at this frequency, i would need to do some tests on hardware to help
<sajattack[m]> it tests up to 150MHz on MiSTer
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<_florent_> do you have a link to the sdram controller used on MiSTer?
<sajattack[m]> it varies by core I think
<sajattack[m]> here's their memtest https://github.com/mister-devel/memtest_mister
<tpb> Title: GitHub - MiSTer-devel/MemTest_MiSTer (at github.com)
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<_florent_> i just tested 100MHz on the De0Nano and got it working with this: https://hastebin.com/apovofubof.rb
<sajattack[m]> oh? two phase shift values?
<sajattack[m]> oh it's a diff
<sajattack[m]> haha
<sajattack[m]> yeah I tried -5000 already
<sajattack[m]> the only numbers I've been able to change are the bus fail and the addr, got up to 64 bus fails, and up to 8192 addr fails
<sajattack[m]> tried probably 20 values in the range 3000-10000
<sajattack[m]> many in the range 4000-6000
<_florent_> with the chip you use (AS4C16M16) CL=2 is fine for clk up to 83MHz, so you should probably test with CL=3
<tpb> Title: litedram/gensdrphy.py at master · enjoy-digital/litedram · GitHub (at github.com)
<_florent_> set cl parameter to 3
<sajattack[m]> oh
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<sajattack[m]> that got it down to 8184 addr fails
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<sajattack[m]> cl=4 got it to 8154
<sajattack[m]> but we can't really just keep increasing it eh
<sajattack[m]> do we need to change some other timings too?
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<_florent_> sajattack[m]: the SDRAM is not supporting CL=4. To investigate, you will have to enable debug: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/sdram.c#L773
<tpb> Title: litex/sdram.c at master · enjoy-digital/litex · GitHub (at github.com)
<tpb> Title: litex/sdram.c at master · enjoy-digital/litex · GitHub (at github.com)
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