<peepsalot>
hi, i'm just starting to learn about litex/migen and curious about how to develop new soft cpu cores. are there currently any fine grained reusable modules that are shared across architectures? i guess I'm picturing some config that defines supported opcodes, and can generate an instruction decoder, modules to define ALUs of various widths and capabilities, L1cache modules etc.
<peepsalot>
i'm also a software dev by trade, and not familiar with HDL yet so this project looks great to me. i've been loath to learn Verilog directly so far as its so ugly
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<gregdavill>
I'm wanting to add a clock domain crossing to ValentyUSB eptri. It currently needs to run in a 12MHz clock domain for the USB side.
<gregdavill>
I want to run my SoC at 48MHz+ and trying to work out the best way/place to add cdc elements.
<gregdavill>
Its interface with the SoC is entirely though CSRs.
<gregdavill>
Is there an easy way to do this?
<gregdavill>
I'm thinking of wrapping the CSRs and using a Async FIFO with address/data/re/we signals. I think this will satisfy the CSR bus cycle.
<gregdavill>
that seems like a better plan than keeping the CSRs in the SoC and breaking out each signal through a separate cdc element to the lower speed domain.
<gregdavill>
Does it? in eptri? I only saw a 'cdc' boolean, that gets passed into the debug bridge. The CSRs and FIFOs look like they always live in the 12MHz domain.
<gregdavill>
I'm attempting to get CircuitPython running. Ideally I want to run it from the SDRAM. But I can't get enumeration, because I think the fetch time in SDRAM is too slow.
<gregdavill>
I think xobs 'solved' this on the Fomu, by moving all time critical stuff into a blockram fro execution.
<xobs>
Oh! Right, CDC. Overloaded acronym. Sorry.
<mithro>
Ahh, only all the *other* interfaces than eptri have CDC
<xobs>
I thought you meant cdc_acm. You mean clock domain crossing.
<xobs>
Right, I wasn't sure how to get cdc working with eptri. That's a longstanding issue. dummyusb has cdc which does, in fact, work correctly.
<mithro>
Yes, clock domain crossing
<mithro>
Just use a FIFO with one end in sys and one end in usb_12
<mithro>
epfifo has an example
<gregdavill>
Okay, I'll have to take a look through the other valentyusb.cpu interfaces, thanks!
<futarisIRCcloud>
CDC = Centres for Disease Control / USB Communications Device Class / Clock Domain Crossing
<futarisIRCcloud>
TLA are not confusing at all.
<mithro>
If you clocks are aligned, you have an even easier time
<mithro>
The fact that flipflops in an FPGA have setup + hold times which (have to) meet your fast clock mean you only need to worry about metastability from clock phase
<mithro>
Another option is to just use a clock-enable strobe
<gregdavill>
Ohh, so the usb_12 is actually clocked at 48, but only has a CE pulse every 4th clock.
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<gregdavill>
That might work well on the ECP5, since it easily meets timing. and it's trivial to setup with a `CEInserter()`
<mithro>
If I recall correctly the capture frontend uses a 48MHz clock with a recovered strobe at 12MHz...
<mithro>
Snap :-P
<mithro>
Writing on my phone while I walk home is slow
<gregdavill>
FYI, I did implement a hardware based USB Communication Device Class. Very much a work in progress, but it's a statemachine that captures the CSR registers and sits behind eptri.
<gregdavill>
I've been using it with linux-on-litex on orangecrab/hadbadge for the UART link. Been working well.
<xobs>
gregdavill: fancy!
<xobs>
another option is to add a uart in litex in "crossover" mode and use `wishbone-tool -s terminal`.
<futarisIRCcloud>
Fancy indeed.
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<peepsalot>
i tried to follow the instructions here https://github.com/litex-hub/linux-on-litex-vexriscv but can't get the sim.py to run. the way the steps are all split up is a bit confusing. the end of prerequisites has cd into the git dir, but are any of the other steps supposed to actually be done inside that directory?
<tpb>
Title: GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv (at github.com)
<peepsalot>
it errors out on compiling xgmii_ethernet.c
<sajattack[m]>
peepsalot if you want I can send you my de10nano build
<sajattack[m]>
You'll need an ftdi cable though
<peepsalot>
sajattack[m]: sure that could be helpful, though i'm also wanting to learn/setup the tools properly.
<peepsalot>
by build you mean like rbf + linux image? where does the linux image go if there's no sd support? its loaded straight to sdram via serial?
<sajattack[m]>
I think your issue might be a non-recursive clone, not sure
<sajattack[m]>
Yes loaded straight over serial via ftdi
<peepsalot>
ok, i think i have one around here somewhere, there's nothing altera specific about the connection device, right?
<sajattack[m]>
no
<sajattack[m]>
just plug into the arduino rx/tx and the pin next to it is grounded
<sajattack[m]>
I think I have to recompile my image, I've been messing with some stuff
<sajattack[m]>
it's the last 3 pins not covered by the io board
<peepsalot>
i have a cp2102
<sajattack[m]>
that should work
<sajattack[m]>
you also need quartus to flash the rbf
<peepsalot>
i forget if its 5 or 3.3v, or configurable somehow. haven't messed with it in a while
<sajattack[m]>
yeah make sure it's 3.3v
<peepsalot>
i have quartus 19.1 installed, tried getting 17.x setup but it wasn't working on ubuntu
<sajattack[m]>
It shouldn't matter, you only need the programmer part and I think it's the same
<sajattack[m]>
gimme a sec to unfuck the stuff I've been messing with
<peepsalot>
yeah looks like its 3.3v data only on the cp2102. i was a little confused because the board have a breakout pin for 5v and 3.3v, but that's just passing the usb rail through
<peepsalot>
sajattack[m]: did you try the simulator at all?
<sajattack[m]>
which part of simulation where you stuck on?
<sajattack[m]>
* which part of simulation were you stuck on?
<peepsalot>
xgmii_ethernet.c:110:8: error: variable 'ret' is used uninitialized whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized]
<peepsalot>
i was just trying to call sim.py and it would automatically start building libraries or something
<sajattack[m]>
yeah but what part is that? what command?
<sajattack[m]>
ok
<sajattack[m]>
oh it's probably because your gcc is newer than what's targeted by litex or something
<sajattack[m]>
I would add -Wno-sometimes-uninitialized to CFLAGS
<peepsalot>
oh, yeah, its running clang-9 :P
<peepsalot>
i haven't flashed with quartus before, and evidently am too dumb to figure this out. you use the usb blaster port? what "mode" for programmer?
<sajattack[m]>
jtag
<peepsalot>
i guess i'm missing usb-blaster driver for linux?
<peepsalot>
ok, i had to change udev rules, looks like it sees it now
<peepsalot>
sajattack[m]: you use the pins corresponding to tx/rx on this image? the pin next to it isn't gnd though? or its configured that way for this specific core?
<sajattack[m]>
the datasheet for that says it supports 1.2M so it might work
<peepsalot>
eh, i just don't know if its putting out 5v signals or not, its capable of either depending on how its connected, but the adapter is overmolded so can't see how its wired up.
<peepsalot>
pain in the butt serial connections
<sajattack[m]>
just try the 500k build then
<peepsalot>
hrm, weird i got litex> prompt but can't type after that
<peepsalot>
using 500000 build
<sajattack[m]>
speed=500000?
<peepsalot>
yes
<sajattack[m]>
it worked for me so idk
<peepsalot>
ok 2nd time worked *shrug*
<peepsalot>
re-uploaded in quartus and connected lxterm again
<peepsalot>
thanks for all the help
<peepsalot>
still uploading image...
<sajattack[m]>
cool glad you got it
<sajattack[m]>
oh btw are you using 32mb or 128mb sdram?
<peepsalot>
128, is that a problem?
<sajattack[m]>
idk
<sajattack[m]>
I've always used 32
<sajattack[m]>
I want to know if it will work with both
<peepsalot>
oh wait, lol actually i have 0 RAM on this board, i guess i should swap it over. i have this separate de10 for learning development and one i use just for mister(with 128MB), forgot about that aspect
<sajattack[m]>
oops
<sajattack[m]>
haha
<peepsalot>
is it not feasible to integrate with the onboard ddr3?
<sajattack[m]>
it's difficult because the hps interface is in the way
<sajattack[m]>
litex doesn't have any knowledge of the hps
<peepsalot>
ok, yeah i know it has to go through hps somehow, but i still don't really understand the details of how that works. isn't the hps over avalon bus, which litex knows about?
<sajattack[m]>
tbh idk
<sajattack[m]>
if you figure it out, send a pr :P
<_florent_>
peepsalot, sajattack[m] : do you have a link to the MiSTer verilog/VHDL code that integrate the HPS? just to have a look at the interfaces.
<peepsalot>
don't really know which cores/where its used exactly
<sajattack[m]>
ok, sorry, how does that fit in with litedram though?
<sajattack[m]>
I can map litex to emu by hand
<_florent_>
this will just allow you to create a LiteX SoC inside the EMU framework of MiSTer, you then have to reuse the interfaces already provided by the EMU framework
<sajattack[m]>
sorry, my question is, how do I get litedram to give me signals for the mister interface? does it already have similar ones?
<_florent_>
the interface in the EMU framework for the SDRAM is a simplified interface, so no need for LiteDRAM, it can probably be easily connected to the wishbone bus
<sajattack[m]>
if I look at another core with ddr, the signals lok different
<sajattack[m]>
ok
<sajattack[m]>
I know very little about wishbone
<_florent_>
you can find useful information about it at:
<_florent_>
line 72 of the template or generated verilog?
<sajattack[m]>
generated verilog
<sajattack[m]>
or line 16
<_florent_>
not directly, you will need to understand the protocol used for the SDRAM interface on MiSTer, how wishbone works and create a bridge between both
<somlo>
_florent_: it just occurred to me (after a week of doing *completely* different things) to actually ask you: what brand of microSD card have you used successfully with liteSDCard on nexys4ddr? :)
<sajattack[m]>
_florent_: could you show me where litedram bridges to wishbone so I can get a better idea of what it looks like for a memory interface?
<somlo>
should have asked a week ago, and ordered the *right* one, and done things in parallel, but that's usually not how it works out for me...