_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<somlo> _florent_, Xiretza: liteeth commit 153c160 causes the linux driver (minimally adapted for 64bit Rocket from the vexriscv driver) to hang during boot
<somlo> I noticed that change was further modified by commit 7a44209, which doesn't fix the behavior I'm observing
<somlo> I'm investigating to see what actually changes in terms of the memory map state before vs. after MACCore initialization that might impact the linux driver (the generated csr.csv file is the same before vs. after the "breakage", so at least "officially" my IRQ numbers, and CSR and MMIO buffer addresses are unchanged)
<somlo> so at first glance it's not that I'm telling the driver to access the "wrong" address(es)
<somlo> which is addmittedly weird, beacause gen.py shouldn't even come into play when building a litex SoC with "--with-ethernet"
<somlo> but weirdly enough, if I check out ec9bc57 (right before ec9bc57) the linux driver loads fine, and, before 7a44209, if *revert* 153c160 the driver also loads fine
<somlo> I'm very confused at this point :)
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<tnt> Would anyone have a link to the vex configuration used in litex to run linux ?
<tnt> Does it use the Linux variant of https://github.com/m-labs/VexRiscv-verilog ?
<tpb> Title: GitHub - m-labs/VexRiscv-verilog: Using VexRiscv without installing Scala (at github.com)
<daveshah> tnt: almost, I think it actually uses https://github.com/enjoy-digital/VexRiscv-verilog
<tpb> Title: GitHub - enjoy-digital/VexRiscv-verilog: Using VexRiscv without installing Scala (at github.com)
<tnt> daveshah: tx.
<tnt> Failing miserably at trying to rebuild those though :/ https://pastebin.com/HrrysXTk
<tpb> Title: nt@ritsuko-ubnt:~/data/vex/VexRiscv-verilog$ sbt compile "runMain vexriscv.GenCo - Pastebin.com (at pastebin.com)
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<somlo> _florent_, Xiretza: looks like I should rely on (my ability to use) git bisect a bit less :)
<somlo> last night I *thought* bouncing around in the liteeth tree made a difference in whether my liteeth linux driver would hang on boot or not, now it hangs no matter what I do in liteeth
<somlo> so I'm taking it all back, I really don't know what (combination of) litex and liteeth recent changes are causing the issue :)
<_florent_> tnt: sorry not sure i can help to generate Vexriscv, i only reused the instructions from @Dolu in the README more than 6 months ago, maybe it's no longer up to date.
<tnt> _florent_: Ah it's ok, got it worked out. Java version was too recent.
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<somlo> _florent_: at least part of my problem might have been using ctrl-r to recall the last litex build command line I had used... Keeping multiple windows open, and logging into and out of the dev vm from many places during the day, I didn't notice I had retrieved the one where I'm asking for a 40MHz clock :)
<somlo> so now I'm trying again with the usual 60MHz, then I'm going bisecting again (if the problem still persists)
<somlo> so, apologies to everyone for the noise, will update if/when I figure out more about what's going on (and how I'm being an idiot) :D
<_florent_> somlo: no problem for the noise. From the quick test i did yesterday, it seems the problem also occurs in simulation, maybe it would be faster to bisect? (lxsim --cpu-type=rocket --with-ethernet --opt-level=O0)
<somlo> _florent_: I'll try both ways, see whether compiling trellisboard bitstream is slower than simulating rocket in verilator :)
<somlo> but thanks for the confirmation -- and now that I'm paying attention to my command line, bisect should hopefully produce something useful :)
<CarlFK> does someone have a URL to the $10 led driver board that has an fpga and 2 gig-e ports?
<somlo> _florent_: ok, so at litex commit #5b34f4cd and liteeth commit #ae10eea it works fine
<somlo> I'll take it from there and see what I can find...
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<scanakci> I am a bit stuck when trying to use tftp to copy files into DRAM. My guess is that it is related to my network configuration (have very limited experience).
<scanakci> This is what I am getting after some time on FPGA.
<scanakci> I followed this link to set up tftp on my machine (https://askubuntu.com/questions/795481/how-can-i-make-my-tftp-server-visible-available-on-my-local-network). Also, I looked into this link to get more info: https://github.com/timvideos/litex-buildenv/wiki/Networking
<tpb> Title: networking - How can I make my tftp server visible/available on my local network? - Ask Ubuntu (at askubuntu.com)
<scanakci> I also put a fake boot.bin file under /tftpboot folder
<scanakci> I connected the ethernet cable to my host machine by using a usb Ethernet Internet Adapter.
<scanakci> The ip for this interface is set (not sure if this is correct)
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<scanakci> it would be great if you can point out some useful links that can help me for setting up tftp properly (or ways to debug where the problem originates from).
<somlo> scanakci: you have to ensure that your host machine has as one of the available IP addresses on the network interface you connected to the fpga
<somlo> the way I do that is "sudo ip addr add scope global dev enp1s0"
<somlo> replace enp1s0 with whatever your network interface is named
<somlo> then, obviously, "systemctl start tftp.service"
<somlo> last, but not least: I tried connecting my laptop with an ethernet cable to the fpga board, and nothing happened
<somlo> some auto-negotiation speed/duplex failure
<somlo> it did work when I used a cheap/generic gigabit capable switch, and connected both the laptop *and* the fpga to it with rj45 cables
<somlo> haven't had a chance to track down why direct point-to-point didn't work (I tried with a straight-through *and* with a cross-over rj45 cable, neither worked, not even after manually hard-coding the speed/duplex settings on the laptop side)
<scanakci> Thank you so much @somlo. I will try it soon.
<somlo> at any point after connecting the fpga to the computer, whether through a switch or directly, you can (should) run a sniffer, e.g. "tshark -i enp1s0 host" to check for any sort of activity
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<somlo> _florent_, Xiretza: seems to work fine (if I pick 60MHz) with current git masters (57fb3720 for litex, 466223e for liteeth)
<somlo> on trellisboard, so I didn't try the simulator
<levi> I'd highly recommend running a sniffer to debug network problems, but be aware that you typically won't see problems below the layer of complete and correct Ethernet frames, and when you're dealing with a FPGA, that's unfortunately a likely layer for errors to occur in. There's a program called `ethtool` that will sometimes let you configure a NIC to accept malformed frames anyway instead of dropping them, but there needs
<levi> to be support in both the NIC and driver for it to work.
<somlo> I spoke too soon, it boots, gets past the linux liteeth driver initialization to the busybox shell prompt
<somlo> but when I try ifconfig on eth0, I get "LITEETH_READER_READY timed out"
<somlo> so that behavior is relatively new, and should be something I can use as a bisect criterion
<somlo> levi: thanks, but it's not really a "network" problem, it's getting Linux to talk to liteeth before driving it to generate network traffic to begin with
<somlo> interestingly, tftp seems to work from the bios (that's how I get my kernel), but then the driver I had that used to work from inside linux is now either hanging during initialization (on boot) or seriously malfunctioning once it got past inititialization
<somlo> it's entirely possible (althoug I'm not sure yet) that the LiteETH "hardware" (RTL) is now *better* than before, and the linux driver needs to be updated.
<scanakci> @somlo: I plug FPGA and my machine to a switch. Also, I did "sudo ip addr add scope global dev eno1". However, still no luck :( .
<scanakci> Unfortunately, could not catch any packet with tshark for
<scanakci> ip addr shows returns this. I assume is one of the available IP addresses on the network interface now https://usercontent.irccloud-cdn.com/file/FOFUIEqq/ipaddr
<somlo> scanakci: for about the last year I've plugged the fpga into a switch port that also has my workstation on a different port, and things worked fine
<somlo> then a few days ago I set up a laptop for a "portable" demo I wanted to do in a conference room, and tried to use a single rj45 cat6 ethernet cable between the laptop's usb-ethernet dongle and the fpga
<somlo> not one single ethernet frame made it across
<somlo> until I plugged them both into a netgear switch, then they started talking :)
<somlo> so there's something (probably on the LiteETH side) that doesn't autonegotiate speed, duplex, or mdi/mdix properly
<somlo> but if you go through an ethernet switch, it works (at least for me)
<somlo> wait
<somlo> you said you did that -- sorry, my reading comprehension is not the greatest today :)
<somlo> and yeah, your ip address lools ok
<daveshah> I've never had any issues with liteeth directly connected to a proper motherboard Ethernet port
<daveshah> With a cheapo realtek USB adaptor I have had issues before, primarily with NFS but once or twice TFTP too
<daveshah> Pretty sure that was just dodgy PC side Linux drivers as much as anything else
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<somlo> daveshah: dodgy pc-side cheapo usb ethernet, passed-through by osx to the linux VM I was using :)
<somlo> the only one I had handy at the time, though (aside from the 4-port netgear switch sitting around in a drawer :)
<somlo> which was really a last-ditch effort to throw something at the wall and see if it sticks -- and it stuck!
<daveshah> In a similar situation I had three different USB ethernet dingles handy and all used the same dodgy chipset
<somlo> that's how cargo-cult style myths are born, I guess...
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