_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
<xobs> acathla: only if you want to contribute! Or make changes to it. There are precompiled binaries in the `releases` section.
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<litex-questions> Hi, I have what I think are two quick CSR related questions.Is there a way to add CSR
<litex-questions> 1. Is there a way to add a CSR from the top-level module?
<litex-questions> 2. Is there a way to add CSRs from grandchildren of the top-level module?
<litex-questions> to be more precise, is there a way to add CSRStatus register for the top-level module (say the SoC). And for the second question, is there a way to add_csr from a submodule's submodule.
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<_florent_> Hi litex-questions, for 1)currently, it's not possible to have the CSR directly in the top-level module, you can create a simple Module, AutoCSR in your top level, add it to the design:
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<litex-questions> Thanks _florent_
<_florent_> For 2), it would be done like this:
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<_florent_> but i would not recommend it since it will not be flexible since you need to know the name of the top_level module in the submodule
<litex-questions> Yea, I basically did the same for both the cases. Was wondering if there was an easier way
<litex-questions> If feels like chaining AutoCSRs is something that would be cool
<litex-questions> and useful
<_florent_> It's already the case, but not in the top-level
<_florent_> add_csr is only required for the module directly instantiated in the top-level
<litex-questions> so you are saying, if a top-level's submodule's submodule has an AutoCSR then it automatically gets added, when I call add_csr in the top module just for the top-module's submodule?
<_florent_> yes exactly
<litex-questions> And what if the top-level's submodule is NOT an AutoCSR?
<_florent_> For the auto-chaining to work, all Modules if the chain needs to be an AutoCSR
<litex-questions> makes sense. Thanks _florent_
<awygle> am i right that CSRs get converted into memory locations on whatever concrete bus the SoC ultimately uses?
<_florent_> awygle: not sure it if answer the question, but the CSRs are collected and connected to a CSR Bus that is bridged/mapped to the main SoC bus
<awygle> interesting. can you say more about the "CSR Bus"? is that a custom litex bus protocol?
<_florent_> That's a very simple bus, a bit similar to APB with limited control signals where reads/writes are expected to be done in 1 cycle. This has been introduced in Milkymist, then reused in MiSoC. The CSR bus in LiteX reusing the CSR Bus from MiSoC, we just made it more generic (to support various data width), added some controls signals (to know when the register is accessed in read) + CSR Fields to ease defining the
<_florent_> mapping of the registers, describe it and allow automatic documentation.
<awygle> i see
<awygle> thank you for the information
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<sajattack[m]> I've asked about ps/2 keyboard suggestions a couple times and haven't got any feedback, anyone have ideas on how best to go about implementing something like that?
<sajattack[m]> my thoughts so far are to share the uart bus but I don't really know how practical that is
<sajattack[m]> for a half-decent mister core I need video, sdcard and keyboard. I got video, sdcard is in progress it sounds like, and now I gotta figure out keyboard
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<_florent_> sajattack[m]: you could reuse a PS2 core and connect it to the UART RX
<_florent_> it seems there was a PS2 core in Milkymist: https://github.com/tmatsuya/milkymist-ml401/blob/master/cores/ps2/rtl/ps2.v
<tpb> Title: milkymist-ml401/ps2.v at master · tmatsuya/milkymist-ml401 · GitHub (at github.com)
<sajattack[m]> ok cool
<john_k[m]> sajattack: are you writing a mister core in litex?
<sajattack[m]> I'm trying to get linux-on-litex running on mister
<john_k[m]> Ahh cool
<_florent_> You could create a wrapper around a PS2 core and add a source as a stream.Endpoint (valid/ready/data)
<_florent_> this way, it will be very easy to connect to the UART
<sajattack[m]> yeah that's kind of what I was thinking
<sajattack[m]> _florent_: there are many ps2 cores out there, any reason you pointed out that one?
<_florent_> sajattack[m]: another PS2 core could probably be used, i just pointed this one since Milkymist's code is minimal and working well
<sajattack[m]> ok, and you suggest I wrap a verilog one, rather than write one in migen?
<_florent_> sajattack[m]: you can write one in migen, that was just to use as a reference since i'm not aware of PS2 code in migen
<sajattack[m]> ok
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<sajattack[m]> I'm pretty new to migen but I'm gonna try
<sajattack[m]> first dumb question, is a signal more like a pin, wire, or reg?
<_florent_> sajattack[m]: you can find useful information here: https://github.com/m-labs/migen/blob/master/migen/fhdl/structure.py#L305
<tpb> Title: migen/structure.py at master · m-labs/migen · GitHub (at github.com)
<sajattack[m]> so it's like wire and reg combined, eh?
<_florent_> yes
<sajattack[m]> what's closest to `input`?
<sajattack[m]> also signal?
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