_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<somlo> daveshah: does a 'nextpnr_ecp5::assertion_failure' with the following message "what(): Assertion failure: closest != BelId() (/builddir/build/BUILD/nextpnr-85f4452b0a3bd47ccb25be023859542ffef888f7/ecp5/pack.cc:2588)" ring any immediate bells?
<somlo> trying to build latest LiteX with Rocket for the trellisboard (or for the versa5g, same issue)
<somlo> I am currently using yosys d448483, trellis 30ee6f2, and nextpnr 85f4452
<daveshah> There was a LiteX change relating to ECLKBRIDGECS
<daveshah> a while ago
<daveshah> I did fix a nextpnr issue related to it but that was also a month or so ago
<somlo> daveshah: it gets weirder -- it builds fine (latest LiteX sources) on the development VM I've been using for a few months and updating
<somlo> but I just built a new VM this morning for a "mobile demo", with the same software (as far as I can tell), and it fails on that one :)
<somlo> so if I had to guess, it's something the whole setup depends on *implicitly* in some way, but I can't for the life of me figure out what
<somlo> at least yosys/trellis/nextpnr/migen/abc/iverilog/verilator are the very same RPMs I've installed on the old (working) VM... :)
<somlo> so if this assertion thing isn't immediately obvious, don't worry about it. It's gotta be some weird quantum Heisen-bug with my setup... :)
<somlo> the downside of having had this happen is that now I'm scared to even breathe too hard in the general direction of my *working* VM :D
<daveshah> It could be to do with an old prjtrellis version being used to build nextpnr
<daveshah> Can you sha256 nextpnr-ecp5 to double check it is the same binary?
<somlo> daveshah: they're different :( Now I gotta figure out how they ended up that way, but this is definitely helpful -- thanks!
<daveshah> It's possible one is built against libtrellis from before libtrellis had ECLKBRIDGECS in it (probably November ish?)
<somlo> oh, I think I know -- I pushed both trellis and nextpnr updates into Fedora to resolve their request to prep for python 3.9
<somlo> and nextpnr must have pulled in the old trellis dependency
<somlo> RPMs on my dev machine are from my local builds, the ones on the new machine are from upstream fedora (which -- good to know -- has a broken nextpnr package, so I should probably rebuild that and push it out again :)
<somlo> also, note to self: in the future, always build trellis first, and wait for it to be published before requesting a nextpnr build :)
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<acathla> Is there a common reason for the litex builder to never finish a build and stay forever in loop?
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<Xiretza> _florent_: fyi, liteeth CI is pretty red due to new_soc
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<_florent_> Xiretza: thanks, i'll look at that
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<_florent_> Xiretza: it's green again :)
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<_florent_> it was green, but has not been re-triggered with litex changes
<Xiretza> ah, makes sense. oh my, such a pretty log, I like it!
<_florent_> thanks, that's really green again now
<_florent_> btw, i'm fine your improvements in #33, do you have others changes you want to do or should i merge?
<Xiretza> _florent_: I'm currently still trying to get customizable mem/csr/interrupt mappings in there somehow, but that's more of a litex thing anyway
<Xiretza> the depths of argparse are not a pretty place
<_florent_> Xiretza: the generator should probably use a .yml config file as the others generator (litedram/litepcie), defining the mem/csr/interrupt map would also be easy this way
<Xiretza> _florent_: yeah, that'd probably be the sanest solution. I'll have a look around.
<_florent_> Xiretza: i could do the skeleton if you want and you could add the configurable mapping?
<Xiretza> sure, if you feel like it, that'd be great. shouldn't be too much trouble to cobble it together myself, but you know your design preferences best :)
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<_florent_> Xiretza: done with https://github.com/enjoy-digital/liteeth/commit/fcadd60ceaa4ac06b2b3ec5c902c8201eebe5cb9, feel free to add parameters if you want to customize the mapping
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