09:53 <xobs> A bit of a historical question: Does anyone know why the litex vexriscv doesn't use standard CSR numbers for things like MIP and MIE? https://github.com/enjoy-digital/VexRiscv-verilog/blob/master/src/main/scala/vexriscv/GenCoreDefault.scala#L208

09:53 <tpb> Title: VexRiscv-verilog/GenCoreDefault.scala at master · enjoy-digital/VexRiscv-verilog · GitHub (at github.com)

09:55 <daveshah> At least historically I don't think it was compliant as it wasn't a standard PLIC

09:56 <xobs> Hmm... I guess the real question I have is: Should I change it back in my designs (i.e. is it compliant now)?

09:57 <xobs> I'm working on Rust support, and I have a forked version of `riscv` that adds `vmim`, `vmip`, `vdci`, `vsim`, and `vsip` calls.

09:59 <daveshah> I haven't followed VexRiscv enough to know

17:47 <rvense> _florent_: i'm havingg trouble getting a working cpu with litex-buildenv for my lattice hx8k evb. the cpu and wishbon bus just lock up. i've been with tim and xobs for a few hours at ccc, and they think it's related to a change you made with how memory regions are set up.

19:13 <_florent_> rvense: can you share the target file of give a link to it?

19:19 <rvense> i just followed https://github.com/timvideos/litex-buildenv/wiki/HowTo-FuPy-on-iCE40-Boards

19:19 <tpb> Title: HowTo FuPy on iCE40 Boards · timvideos/litex-buildenv Wiki · GitHub (at github.com)

19:19 <rvense> so https://github.com/timvideos/litex-buildenv/blob/master/targets/ice40_hx8k_b_evn/base.py

19:19 <tpb> Title: litex-buildenv/base.py at master · timvideos/litex-buildenv · GitHub (at github.com)

19:20 <mithro> _florent_: we have discovered that it is happening because nothing is mapped to address 0

19:21 <rvense> commit 96ab220b0f60e3d509ca0a66dcfb81676ef294d9 produced a working image

20:21 <_florent_> mithro, rvense: ok, i'll look at that

23:45 <futarisIRCcloud> https://twitter.com/pdp7/status/1210885427336495104?s=19

23:46 <futarisIRCcloud> QwertyEmbedded: All I had to do was sleep.