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<somlo> has anyone managed to build a versa_ecp5 SoC with working Ethernet recently? I'm using yosys 613334d, trellis 4e0b215, nextpnr dd7f7a5 (built on Dec. 11), and the most recent LiteX
<somlo> no matter whether I try to build a Rocket system at 60 MHz or a vexriscv at 75MHz, when it tries to tftp-boot "bios.bin", the tftp server sees the requests and replies to them, but the ecp5 board acts like it never receives any return traffic, and fails out of netboot
<somlo> _florent_, daveshah: ^^^^
<daveshah> With whatever Yosys nextpnr and LiteX I have (circa a week or two old) it seems alright
<somlo> daveshah: do you have a copy of the bitstream you could share -- so I can rule out *physical* hardware and networking?
<somlo> daveshah: nvm, I grabbed a really old one I had from months ago, and it tftp's just fine
<somlo> it's gotta be at the intersection of my specific toolchain, litex, and liteeth version
<daveshah> Sorry, got hit by a power cut which briefly took out the phone masts too
<daveshah> Will continue looking once power is back
<daveshah> So as far as I can tell, with latest Yosys and nextpnr, it is fine
<daveshah> that was with LiteX 3d20442f and liteeth f2b3f7ee
<daveshah> Seems to work fine with latest LiteX too
<somlo> ok, maybe I landed on a weird yosys+nxtpnr combination, let me try to rebuild both from latest sources, see if that changes anything for me...
<somlo> well, just yosys, since both my trellis and nextpnr are at their latest github versions...
<somlo> daveshah: http://mirror.ini.cmu.edu/top.svf (built using yosys f52c6ef, trellis 4e0b215, nextpnr dd7f7a5, and current litex/liteeth/litedram)
<somlo> command was "litex/litex/boards/targets/versa_ecp5.py --gateware-toolchain trellis --sys-clk-freq 75e6 --with-ethernet --cpu-type vexriscv"
<somlo> if you get a chance to try it on a 5g versa and tell me if ethernet works for you -- because it still won't for me :(
<daveshah> somlo: works fine here...
<somlo> ugh... works fine here with my *other* versa5g board... What I don't get then is why that really old bitstream I tried on the "broken" one *did* work...
<somlo> anyhow, me and my weird hardware heisen-bugs, sorry for all the noise :)
* somlo needs to add "try another board" into his troubleshooting workflow :)
<daveshah> Guess it is something marginal around the RGMII link to the phy
<_florent_> somlo: it could be worth adjusting the delays values of the DELAYF:
<tpb> Title: liteeth/ecp5rgmii.py at master · enjoy-digital/liteeth · GitHub (at github.com)
<tpb> Title: liteeth/ecp5rgmii.py at master · enjoy-digital/liteeth · GitHub (at github.com)
<tpb> Title: liteeth/ecp5rgmii.py at master · enjoy-digital/liteeth · GitHub (at github.com)
<_florent_> i haven't played that much with it since the expected values were working, but this would maybe need some adjustements to be more reliable
<somlo> _florent_: thanks, I'll try playing with that next time I plug in the *other* versa board :)
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