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<acathla> _florent_, it works! Thank you
<acathla> Now, I can write to the uart, read the first char available on rxtx, but not the following chars...
<acathla> oh, just found it, a bit by chance.
<_florent_> acathla: ok so you are doing that in simulation?
<acathla> I'm testing an uart on the wishbone bus through an UART-wishbone bridge. The goal is to test a modified uart to do infrared communication
<tpb> Title: RFC: update liteeth driver to automatically calculate hwreg offsets by gsomlo · Pull Request #60 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)
<somlo> _florent_: it seems csr subregisters show up in native CPU endianness when dumped with the `mr` command from the bios prompt
<somlo> which is great when writing software, not complaining, but a bit unexpected -- I thought they'd be stored the same way regardless of the CPU endianness. Am I missing something?
<_florent_> acathla: ok good
<_florent_> somlo: thanks for the investigation, i need to look at the code to answer, i'll try to do that later today
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