01:22 <somlo> _florent_: I think I'd like to have a 128bit *and* a 256bit version of the Linux variant, since there are boards that support 128 bit liteDRAM natively (versa5g) and 256 (trellis), in addition to 64 (nexys4ddr).

01:23 <somlo> so I'll add those to the pre-built verilog submodule at some point soon, then to the litex rocket core.py file

01:25 <somlo> I think data-width conversion should be available, but as a backup if matching rocket/mem-axi and litedram-port widths is not an option for some other reason