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<keesj> Hi
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<somlo> daveshah: just a heads-up, I bumped yosys, trellis, and nextpnr to their respective freshest commits available on github
<somlo> and the yosys transition from #81876a3 to #db22687 is doing something weird to litex/rocket on the trellisboard
<somlo> I have an as-of-yet uncommitted 256-bit-wide mem-axi rocket variant, and the symptom is that memtest passes, bios runs, and the tftp transfer completes, but once the BBL tries to start running the linux kernel, it just "hangs"
<somlo> sorry, that is the level of detail I have right now :)
<somlo> with the older yosys, the kernel loads, busybox runs, and all is happy
<somlo> with the newer yosys, it just hangs after BBL hands over control to linux
<daveshah> Do you think you'd be able to bisect?
<somlo> tried leaving out "--nowidelut", but that just stops memtest from passing altogether
<somlo> yes, I will bisect, but tomorrow (or later this evening, US EST :) -- bad weather incoming, outstanding yard work :)
<somlo> bisect should be simple (although maybe a bit time consuming), since I don't have any special patches to deal with right now, it's just straightforward upstream commits
<somlo> the reason I haven't committed the wide axi-mem rocket variants yet is that I'm waiting for an upstream fix to something I have to patch manually right now: https://github.com/chipsalliance/rocket-chip/issues/2168
<tpb> Title: commit #f31e21b5b breaks yosys synthesis · Issue #2168 · chipsalliance/rocket-chip · GitHub (at github.com)
<somlo> but that's neither here nor there :) Just wanted to see if you had an immediate prime suspect
<somlo> oh, another "high-level" symptom is that it works if I use a narrow Rocket version with the wishbone-based converter, only hates it when I do native point-to-point (wide) AXI between rocket and litedram
<somlo> anyhow, yardwork, then bisect, and I will let you know once I have something a bit more useful and actionable :)
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