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xobs >
_florent_: would those Wishbone changes you made affect the ability to use the vexriscv debug bridge?
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13:58
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daveshah >
Trying to build latest linux-on-litex-vexriscv for versa and I'm getting some compile issues. I think everything is up to date.
13:58
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daveshah >
Seems like these are now lowercase in generated/csr.h?
14:03
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daveshah >
After changing the uses of those macros to lowercase, it builds and works fine. But I don't think this is really an intended change
15:32
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somlo >
daveshah, _florent_: getting the same thing when building rocket (for ecp5versa and nexys4ddr)
15:45
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somlo >
commit 8be5824e is the "culprit", apparently
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tpb >
Title: [WIP] ecp5: Add support for mapping 36-bit wide PDP BRAMs by daveshah1 · Pull Request #1425 · YosysHQ/yosys · GitHub (at github.com)
15:50
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daveshah >
if you have a chance
15:52
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somlo >
daveshah: oh, so xc7dsp got merged, and these are fixups on top of it... cool!
15:53
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somlo >
I'll try them sometime today and report back (got dragged into some unrelated work over the last couple of weeks, gotta catch up with what happened while I wasn't paying attention :)
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somlo >
I should probably turn this into a proper litex PR
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tpb >
Title: soc/integration: ensure CSR constants are in uppercase by gsomlo · Pull Request #270 · enjoy-digital/litex · GitHub (at github.com)
16:30
* somlo
is off doing a complete toolchain update from github: trellis, nextpnr, and yosys
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xobs >
What kinds of pitfalls will I run into if I have a device on Wishbone that's in a different clock domain? And how is arbitration handled?
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_florent_ >
somlo, daveshah: thanks for catching the case issue, it's merged
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_florent_ >
xobs: i haven't really touched wishbone the the last days, i was mostly trying to cleanup SoCCore
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