I don't know if you or I should send a PR, or maybe _florent_ can just fix that when he gets to catch up with his IRC log :)
daveshah: thanks for tracking that down, in the mean time my build is cooking again :)
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my fomu arrived \o/
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Working on adding iceFUN board to litex-buildenv. No problems with gateware+bios+none using lm32 softcpu on harware, but when switching to vexriscv, I can't even hit bios over serial. Tim suggested that wishbone-tool might be a starting point for debugging. I seem to be able to peek with it but the results seem inconsistant. Any help or suggestions
on what to try next would be great.
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kbeckmann: thanks for the feedback, for nMigen, we'll have to evaluate the pros and cons, for now the actual codebase does not have enough unit-tests to be able to do the switch easily, so i'm trying first to improve that and simplify things. Some of the LiteX features/tools also heavily rely on Migen internals, and i haven't evaluated how much rewrite needs to be done to be able to have the similar features/tools
with nMigen. At least, it will be possible to have Migen/nMigen modules cohabitate in the same LiteX SoC design. (nMigen modules could be elaborated during the build automatically and reintegrated as Migen verilog instances).
somlo, daveshah: i'm looking at the --uart-name issue
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daveshah: i've been able to get SerDes TX/RX working on ECP5 today (using whitequark's pcie work as a basis), the open-source toolchain is really a time saver for this kind of work! (iterations in a few seconds vs minutes when i was doing similar work for Xilinx).