tpb has joined #litex
John_K has quit [*.net *.split]
John_K has joined #litex
freemint has quit [Ping timeout: 245 seconds]
freemint has joined #litex
freemint has quit [Ping timeout: 245 seconds]
_whitelogger has joined #litex
_whitelogger has joined #litex
freemint has joined #litex
_whitelogger has joined #litex
freemint has quit [Remote host closed the connection]
freemint has joined #litex
ambro718 has joined #litex
<somlo> daveshah: I've finally grabbed my other board, and programmed it with the 65MHz rocket bitstream I finished with yesterday afternoon
<somlo> this board appears to pass memtest without any failures, on a reliable basis
<somlo> whereas the other board failed about 50% of the times I used the reset switch, but mostly worked reliably when pusing the bitstream anew via openocd
<somlo> so, I'm inclined to assume a manufacturing/tolerance issue
<somlo> now, out of curiosity, I need to figure out what the slowest clock speed is that I can use on this "better behaved" board :)
<somlo> daveshah: your "old" picorv32 75MHz bitstream fails both at openocd push and at reset about 4/5 times; the "new" one (second one you gave me yesterday) succeeds 4/5 times
<somlo> my own rocket bitstream also succeeds almost every time I reset, or push, haven't had it fail on my yet
<somlo> _florent_, daveshah: on a semi related note, making rocket's mem_axi port 256bit wide, to perfectly match the tellis board, will also cause it to no longer fit on the versa :(
<somlo> so, I'm thinking, leave the standard/linux/full variants as-is for now (full won't fit on the trellis board either, only on the nexys, whose litedram port width is 64)
<somlo> and *add* a new rocket variant, linux-trellis (I'm happy to take suggestions on a better name for the variant :)
<somlo> with 256bit mem_axi, and a bit more L1 cache (which also won't fit on the versa, but for which there seems to be some room left on the trellisboard)
<somlo> of course, I'll have to wait for the rocket folks to fix the firrtl emitter yosys synthesis bug I found yesterday, before I can officially push an update to litex-rocket-verilog
<somlo> but, as much as I didn't want to add yet-another-variant, I think it only makes sense...
<somlo> fresh board also mostly stable at 60MHz (one reset memtest failure in about 10 attempts)
<somlo> now trying at 55MHz (this is with the rocket bitstream)
<somlo> daveshah: fails memtest consistently at 55MHz
<somlo> but 60 and up is pretty reliably OK, so given that the "official" number is 75, I wouldn't call it "unreliable"
<somlo> ok, now back to fiddling with Linux :)
CarlFK has quit [Remote host closed the connection]
CarlFK has joined #litex
rohitksingh has joined #litex
rohitksingh has quit [Ping timeout: 250 seconds]
freemint has quit [Remote host closed the connection]
freemint has joined #litex
freemint has quit [Ping timeout: 245 seconds]
freemint has joined #litex
CarlFK has quit [Quit: Leaving.]
scanakci has quit [Quit: Connection closed for inactivity]
freemint has quit [Ping timeout: 245 seconds]
freemint has joined #litex
Dolu_ has joined #litex
Dolu has quit [Ping timeout: 268 seconds]
Dolu_ is now known as Dolu
CarlFK has joined #litex
tpb has quit [Remote host closed the connection]