I have a question related to testing strategy that we should have for integrating a cpu in litex. We figured out how blackparrot off-chip link interface looks like and currently writing a convertor to adapt the BB memory interface to wishbone(BP2WB). Soon, we would like to test Blackparrot&BP2WB convertor and see if communication between BlackParrot core and Litex DRAM goes correct. Blackparrot repo has some basic
helloworld testbenchs, so I was planning to use one of those as a first step in Litex. Is this straightforward? litex_sim seems to run BIOS for current CPUs and I think it is a bit aggressive test for first shot. Any feedback, suggestion will be so helpful.
CarlFK has joined #litex
Where is the best place to set the ethernet MAC address to a static address (instead of a random MAC each time fpga is programmed)?
ambro718 has joined #litex
ambro718 has quit [Quit: Konversation terminated!]
somlo: i'll try to see if i can add an AXI converter in the next weeks (this will also be useful for the others CPUs using AXI)
scanakci: for the first tests, you can
you can use litex-sim with --rom-init to use you software instead of the BIOS
you can also trace the signals by adding --trace
once you have the bios working and want to test with LiteDRAM in simulation, use --with-sdram and it will use a SDRAM instead of the integrated main_ram
it's static for now, but we could make it configurable and loaded from an EEPROM or SPI Flash
CarlFK has quit [Ping timeout: 240 seconds]
_florent_: looks pretty straightforward to specify the mem_axi data_width on the rocket verilog side (even independently of the mmio_axi data_width!)
but rather than a cpu-type x mem_axi_datawidth matrix of pre-generated verilog, it'll be nice to have a rocket with mem_axi datawidth set to the widest LiteDRAM configuration (128bit on the versa, gotta find out about trellis), and down-convert for boards where it is narrower
forksand has quit [Read error: Connection reset by peer]
John_K / mithro / _florent_ : Looks like DDR2 on Pano Logic just got solved recently. cryozap and ali_as were talking about it on ##fpga.