<whitequark>
well, I do support python 2, but it does have new style classes anyway
<whitequark>
it just wasn't clear at all why there's the disctinction or what one should use
<whitequark>
... why is it not possible to do def x(y, (z, t)): anymore in python 3?..
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<ccube>
how do I know what and where the limitation of the uart max baud rate is. I am getting pretty much weird results. If I am setting the baud rate in software, I can get as high as 115200*10, whereas setting it in hardware in synthesis time, transmittin seems to be working way faster, but when trying to reiceive data, some bytes always get lost! :(
<sb0>
are you sure that there is a difference between setting it at synthesis time and in software?
<sb0>
or are you just seeing noise?
<sb0>
the ccc camp "failosophy" topic sounds pretty lame.
<sb0>
guess i still won't go this year...
<sb0>
infosec obsession is the actual problem, not criticism
<ccube>
sb0, not sure. I changed to things at the same time. The problem could also be, that I am not booting from BIOS anymore, but loading my program directly
<ccube>
but anyway, the whole behaviour is kind of strange and Id like to know why
<sb0>
you may need rigor for that. fpga tools are tricky...
<ccube>
rigor?
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<sb0>
if you think that there is a difference syntesis time vs. runtime, test that carefully enough times...
<ccube>
ah, kk
<ccube>
i gonna try harder :D
<ccube>
okay, looks pretty much that 115200*10 is my limit. what might be the limiting factor here? cpu frequency?
<sb0>
what happens above the limit? data corruption? slow cpu shouldn't cause that, no
<sb0>
if it's on papilio pro, it could be signal integrity issues. we found the pcb layout to be pretty bad in that respect.
<sb0>
or bugs in the uart code, or the ftdi-chip
<whitequark>
10MHz uart? is it even supposed to work that fast?
<sb0>
1.1...MHz
<whitequark>
oh
<whitequark>
right, that should work
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<ccube>
sb0, yeah, it might be data corruption and/or data los. it is hard to say what exactly happens. what board would you recommend instead of the ppro?
<ccube>
if i try with 115200*11 or higher, it feels kind of that there is no sync between the devices. almost not receiving anything then. if I am at 115200*10, sometimes a byte gets lost and therefore my communication is messed up. I am currently trying to transfer the 1.1GB of data with 115200 to see if it runs through without loss
<ccube>
will need a couple of hours, though. :/
<GitHub193>
[artiq] sbourdeauducq pushed 4 new commits to master: http://git.io/vvJZb
<GitHub193>
artiq/master fb75bd2 Sebastien Bourdeauducq: targets/kc705: make AMP the default
<GitHub193>
artiq/master 24b2bd7 Florent Kermarrec: soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds
<GitHub193>
artiq/master bdd02a0 Florent Kermarrec: targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :)
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<travis-ci>
m-labs/artiq#105 (master - 601f593 : Sebastien Bourdeauducq): The build has errored.