sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<sb0>
not sure how optimized the xilinx par is...
hozer has joined #m-labs
hozer1 has quit [Ping timeout: 264 seconds]
bentley` has quit [Ping timeout: 255 seconds]
bentley` has joined #m-labs
ohama has quit [Ping timeout: 248 seconds]
ohama has joined #m-labs
ohama has quit [Disconnected by services]
ohama has joined #m-labs
ohama has quit [Ping timeout: 245 seconds]
ohama has joined #m-labs
ohama has quit [Disconnected by services]
ohama has joined #m-labs
ohama has quit [Ping timeout: 276 seconds]
ohama has joined #m-labs
<GitHub132>
[misoc] enjoy-digital pushed 2 new commits to master: http://git.io/vf1xr
<GitHub132>
misoc/master ae71bf2 Florent Kermarrec: liteeth: fix and improve 10/100/1000Mbps speed auto detection
<GitHub132>
misoc/master 07b7c2a Florent Kermarrec: liteeth/phy/gmii: add default value for pads_register
ohama has quit [Remote host closed the connection]
ohama has joined #m-labs
<GitHub17>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/vfMja
<GitHub17>
misoc/master 0b1a2e1 Florent Kermarrec: liteeth: do MII/GMII detection in gateware for gmii_mii phy
stekern_ has quit [Ping timeout: 264 seconds]
stekern has joined #m-labs
<cr1901_modern>
TIL it's also possible to program a CPLD or FPGA using a microcontroller's GPIO pins. Well, specifically, it's well-documented how to do that. I thought it was vendor-specific/proprietary
<whitequark>
xilinx documents bitstream format for some FPGAs
<whitequark>
spartan 3e iirc
<cr1901_modern>
I'm reading the following appnote: http://www.xilinx.com/support/documentation/application_notes/xapp058.pdf Xilinx calls the format Serial Vector Format. I guess it includes "generic JTAG operations", and embeds the bitstream-specific data as operands for those generic JTAG ops
<cr1901_modern>
In any case, I really need to learn how to play with JTAG, so this is a good place to start as any