<cr1901_modern>
that's... interesting. Coming from C-include land I'd probably just import OrderedDict in all modules that need it. Seems like that could cause some interesting uintended results tho.
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<GitHub127>
[artiq] whitequark pushed 3 new commits to new-py2llvm: http://git.io/vLTGt
<GitHub127>
artiq/new-py2llvm d27bb31 whitequark: Add support for ListComp.
<GitHub127>
artiq/new-py2llvm dbfdbc3 whitequark: Add check for duplicate parameter names.
<GitHub127>
artiq/new-py2llvm 20e0e69 whitequark: Add support for function types and LambdaT....
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<GitHub9>
[artiq] whitequark pushed 2 new commits to new-py2llvm: http://git.io/vLkai
<GitHub9>
artiq/new-py2llvm 7a00a4a whitequark: Fix typo in a test.
<GitHub9>
artiq/new-py2llvm a378986 whitequark: More friendly artiq.py2llvm.typing testbench.
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<GitHub159>
[artiq] whitequark pushed 1 new commit to new-py2llvm: http://git.io/vLkFx
<sb0__>
ysionneau: the artiq_flash looks for the .bit bitstream but you are packaging .bin
<sb0__>
ysionneau: also, getting the flash proxy bitstreams is a mess right now. fix that.
<rjo>
ysionneau did not start the mess with getting and maintaining the proxy bitstreams. that is a bad choice in migen. ;)
<rjo>
... and xc3sprog etc.
<sb0__>
well, how would you do it?
<rjo>
quick fix would be to get the bitstreams shipped with xc3sprog and then later dump xc3sprog and do it right.
<ysionneau>
how about doing a conda package with all flash proxies + the xc3sprog binary?
<ysionneau>
when you say that "now it's a mess", it's because you need to fetch one flash proxy from rjo's web server (pipistrello) and one that you need to compile yourself (kc705)?
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<cr1901_modern>
ysionneau: Do you have a moment to answer a question?
<ysionneau>
cr1901_modern: just ask directly :)
<cr1901_modern>
lol... looking at migen's wishbone module, I've noticed that it's possible to create a wishbone slave without resorting to an FSM (by just ensuring ACK_O is asserted for a single cycle after CYC_O and STB_O are asserted). >>
<cr1901_modern>
Do you know if it's possible to generate a wishbone master in a similar manner without an FSM?
<cr1901_modern>
(See SRAM in wishbone.py for example)
<cr1901_modern>
Actually nevermind, I think I figured it out o.0;
<ysionneau>
hehe, sometimes just formulating a question gives you an answer
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<cr1901_modern>
Well, looks like I did my wishbone controller for SRAM at least partially wrong- the default memory controller is for write-first memories o.0;
<cr1901_modern>
(which tbh, I'd never heard of until I started reading specials.py)
<cr1901_modern>
ysionneau: I retract my previous statement. I don't think what I'm trying to do is possible for either master or slave. It works for the SRAM in wishbone.py b/c it's write-first
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<sb0__>
ysionneau: yes.
<ysionneau>
so, if I embed the proxies in the artiq conda package (but fixing the fact that I've put the .bin instead of the .bit) then it's OK?
<sb0__>
yes
<ysionneau>
ok, sorry, was not clear to me, now it is
<ysionneau>
so this simplifies the "fetching proxies" for the "install from conda" part.
<ysionneau>
then, in the "install from sources", is it OK if it remains like that? (fetching one from rjo's web server, fetching the other from my webserver, or his whatever)?
<ysionneau>
or does it need somehow to get simplified as well?
<sb0__>
ok to leave install for sources as is. better if you can find out how to rebuild the pipistrello bitstream.
<sb0__>
the kc705s do not boot and I'm not sure if that's the reason (I modified artiq_flash to simply look for the .bin file, but data could be incorrect)
<ysionneau>
does the FPGA configures correctly when pushing the flash proxy?
<sb0__>
yes
<ysionneau>
ok, maybe mine is not functional, I honestly didn't test it
<ysionneau>
I built it from rjo's repo
<rjo>
i never tested the kc705 proxy bitstream from my repo. only pipistrello and ppro
<ysionneau>
right now I can't fire up my build machine to generate the .bit, so if you need a very urgent quick fix I can just push the modification you did to artiq_flash, if it's less urgent I can have a look tomorrow morning. But that does not fix the "not booting" issue.
<ysionneau>
oh!
<ysionneau>
ok, so which one is supposed to work?
<sb0__>
that modification may not work.
<rjo>
for kc705 i only ever tried the one that was floating around (the vhdl one iirc)
<sb0__>
ysionneau: why not package the .bit?
<ysionneau>
I think it's just a mistake, I took the wrong file, but I don't have access at this hour of the night to the computer where I can build the bitstream
<ysionneau>
and I don't have the .bit on my laptop
<ysionneau>
but tomorrow morning I can have a look at my desktop computer, and package the .bit
<ysionneau>
but, anyway, I thought this repo was 'known to be working' to flash kc705
<GitHub58>
[artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vLqDx