00:56 <sb0> ysionneau, it should be consistent with what artiq_client does

13:48 <GitHub62> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/vLWrt

13:48 <GitHub62> migen/master f8b1152 Florent Kermarrec: wishbone: add Cache (from WB2LASMI)

13:50 <GitHub77> [misoc] enjoy-digital pushed 2 new commits to master: http://git.io/vLWov

13:50 <GitHub77> misoc/master c0bc94c Florent Kermarrec: soc/sdram: add capability to share L2 cache in multi-CPU SoCs

13:50 <GitHub77> misoc/master 3b9f287 Florent Kermarrec: sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon

13:52 <ysionneau> next step add an IOMMU for wishbone accesses to remap/authorize/deny accesses

13:53 <ysionneau> :p

14:30 <sb0> _florent_, what does this do? https://github.com/m-labs/misoc/blob/c0bc94ca1c54da49370ffa15c0ba27521ce92759/misoclib/soc/sdram.py#L57

14:31 <sb0> ah, got it. register_mem will connect a master on the interface.

14:32 <GitHub23> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/vLWNN

14:32 <GitHub23> misoc/master 7c2d0fa Sebastien Bourdeauducq: indentation

14:33 <sb0> looks good.

14:36 <sb0> _florent_, I would create wb_sdram in amp.KernelCPU instead of soc.AMPSoC

14:37 <sb0> the reason we are passing LASMI interfaces to the cores that drive them is because there are parameters from the LASMI interface that configure the core, whereas the KernelCPU will only take 32-bit regular Wishbone

14:38 <_florent_> OK I can change that, and the add_wb_sdram_if do you want it in AMPSoC or KernelCPU?

14:39 <sb0> AMPSoC

14:39 <sb0> makes the KernelCPU more self-contained.

14:40 <_florent_> OK I'll do that

14:40 <sb0> thanks >)

14:40 <sb0> :)

14:40 <GitHub147> [artiq] fallen pushed 1 new commit to master: http://git.io/vLWjH

14:40 <GitHub147> artiq/master afc7092 Yann Sionneau: artiq_coreconfig: use subparsers for arg parsing

14:42 <sb0> _florent_, besides those small details it looks good, if you can still run and talk to the kernel CPU you can commit directly

14:44 <_florent_> OK

14:44 <sb0> oh and i guess mailbox.c should not flush l2 anymore

14:47 <GitHub68> [artiq] fallen pushed 1 new commit to master: http://git.io/vLlJ9

14:47 <GitHub68> artiq/master 250f9e0 Yann Sionneau: manual: update artiq_coreconfig parameter's syntax

23:22 <cr1901_modern> sb0: Can I email you a trivial patch directly so I don't waste space on the mailing list?

23:22 <cr1901_modern> It just removes the dependency on bash for Windows users when running Xilinx tools. It does not affect Linux users. (Migen)