<cr1901_modern>
This might be a stupid question, but... how do JTAG based programmers that talk directly to the FPGA load a bitstream into nonvolatile storage (or "they don't?"). ISF seems to only be used to place data AFTER the bitstream in flash.
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<ysionneau>
rjo: ack
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<GitHub112>
[artiq] fallen pushed 1 new commit to master: http://git.io/vtwqA
<GitHub112>
artiq/master 515aa96 Yann Sionneau: controllers: use --simulation for simulation
<sb0>
whitequark, what exactly do you have in mind with "memory safety necessary for stack allocations"?
<whitequark>
I've described it yesterday...
<whitequark>
well, exactly? add a type parameter that contains a region. literally a source range during which the allocation is valid
<whitequark>
on unifying, the subtyping relation is enforced. a :> b would mean that b is included in a
<whitequark>
that is all
<sb0>
ah, that region system
<whitequark>
rust has borrow checker, which makes the system incredibly complicated, but we won't
<whitequark>
and the basic one is very straightforward
<sb0>
"memory safety" sounded like a MMU or something like that
<whitequark>
ah
<whitequark>
don't need an MMU with a memory-safe language :p
<sb0>
are you going to check array bounds?
<whitequark>
yes
<sb0>
ok
<whitequark>
I shouldn't?
<whitequark>
or rather, is there any reason I shouldn't?
<sb0>
no, that's fine. as long as it isn't slow...
<whitequark>
LLVM can hoist that out of loops, even
<whitequark>
shouldn't be more than 1% slowdown or so
<whitequark>
based on what I've seen in other LLVM-based langs
<sb0>
sounds good
<sb0>
and I guess you can throw a IndexError exception on a invalid access?
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<rjo>
sb0, whitequark: do you two feel that a bit of discussion about pythonparser/new-py2llvm would help? forging a bit of a roadmap prioritizing, which features land when, implementation things etc. do you feel that somebody should dive into these things (compiler desgin related stuff is certainly new to me)?
<GitHub120>
[artiq] fallen pushed 2 new commits to master: http://git.io/vtoNZ
<GitHub120>
artiq/master a73776b Yann Sionneau: controllers: enforce the usage of either --simulation or --device
<GitHub120>
artiq/master ffe1355 Yann Sionneau: lda_controller: improve help message for --device argument
<rjo>
ysionneau: btw: if you mention "closes #24" (or any other similar wording) in the changelog entry, it will close that thing automagically.
<rjo>
sb0, ysinneau: I'll add a few __all__s to the artiq.language area to streamline the namespace a bit.
<rjo>
whitequark: ack. just wondering. i am not certain discussing this is absolutely necessary, especially since i would need to dig into the theory a bit before.
<whitequark>
rjo: it was my intent to discuss the transforms as well, since while I understand how they currently work, I'm not sure what is the intent behind all that code
<whitequark>
and this needs to be done before codegen, or at least parts of codegen
<whitequark>
since the design of codegen would depend on that. e.g. whether there should be an AST-to-CFG phase before codegen
<whitequark>
it's needed for a clean implementation of inlining, but it's not clear that the inlining itself is necessary, and if not, it would be best to get rid of it
<GitHub149>
[artiq] jordens pushed 1 new commit to master: http://git.io/vtKSg
<GitHub149>
artiq/master 3ee2bd5 Robert Jordens: pipistrello: set CLKFX_MD_MAX from MD ratio
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<travis-ci>
m-labs/artiq#268 (namespace_all - 0abea0c : Robert Jordens): The build passed.
<rjo>
cr1901_modern: you first load a jtag-to-spi proxy bitstream onto the fpga through jtag and then talk to the spi flash behind the fpga through that proxy and program the flash.
<cr1901_modern>
Ahhh, that makes sense. How does JTAG actually access the SPI driver inside the FPGA? Is there a JTAG extension that lets you write to a memory cell defined in the proxy bitstream that connects to the SPI driver
<rjo>
you instantiate a bscan cell that gives you access to the jtag lines.
<cr1901_modern>
Not really interested in the money (I'd rather do this at my own pace)
<cr1901_modern>
rj0: Can you elaborate on why openocd and flashrom do not "cover the full scope" of applications?
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[migen] fallen pushed 1 new commit to master: http://git.io/vtiml
<GitHub46>
migen/master 4509265 Yann Sionneau: travis: use use-local for conda install...
<cr1901_modern>
For my current dev board, the programmer doesn't actually use JTAG- it bit-bangs an SPI serial interface to flash, and so can serve the dual purpose of programming a bitstream and flashing user code afterward
<rjo>
i have not seen openocd used with a clean proxy bitstream to program flash for s6.
<rjo>
flashrom does not really concern itself with the jtag side of things that much
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<rjo>
having a slightly more powerful jtag is pretty cool because you can also debug you soft-cpu on the fpga with it, or build a uart over jtag.
<cr1901_modern>
"debug you soft-cpu"... don't vendors let you do that already?
<rjo>
vendor of what? you have to get the jtag signals from your soft cpu to somewhere.
<cr1901_modern>
I meant FPGA vendors, but ignore the question.
<cr1901_modern>
It's not well-formed XD
<cr1901_modern>
I thought JTAG: 1. Does boundary scan, 2. Allows you an interface to program a design, 3. provides vendor specific extensions for debugging the FPGA.
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<rjo>
all correct. one of the extensions is a virtual jtag tap that you can hook up to your soft cpu. if your jtag tools understand this stack (jtag hw, fpga, virtual tap, cpu) you can do some nice tricks.
<cr1901_modern>
rj0: Oh I see... essentially, use the FPGA's JtAG capabilities to give a custom CPU design JTAG capabilities as if you has a custom CPU ASIC with JTAG capabilities
<rjo>
yes
<rjo>
but that is only one thing you can do with it. you can also add a little jtag-to-uart translator next to it. thus through one port you get access to the fpga configuration, the spi flash, the cpu jtag, a debug uart.