00:30 <GitHub116> [smoltcp] whitequark commented on issue #262: @m-labs-homu r+ https://github.com/m-labs/smoltcp/pull/262#issuecomment-417819440

00:30 <GitHub41> [smoltcp] m-labs-homu commented on issue #262: :pushpin: Commit a6d364a has been approved by `whitequark`

00:30 <GitHub175> [smoltcp] m-labs-homu force-pushed auto from 094c6cb to 2acd13f: https://github.com/m-labs/smoltcp/commits/auto

00:30 <GitHub175> smoltcp/auto 2acd13f jhwgh1968: Add iter_data() to Assembler...

00:30 <GitHub70> [smoltcp] m-labs-homu commented on issue #262: :hourglass: Testing commit a6d364a2ccfdc59d5c4e644b6fe49c01c51b8215 with merge 2acd13fe8b54ccac4f4b62158845c767b47f4b49... https://github.com/m-labs/smoltcp/pull/262#issuecomment-417819467

00:39 <GitHub80> [smoltcp] m-labs-homu merged auto into master: https://github.com/m-labs/smoltcp/compare/51eb71784fab...2acd13fe8b54

00:39 <GitHub122> [smoltcp] m-labs-homu closed pull request #262: Add iter_data() to Assembler (master...assembler-iter) https://github.com/m-labs/smoltcp/pull/262

00:39 <GitHub12> [smoltcp] m-labs-homu commented on issue #262: :sunny: Test successful - [status-travis](https://travis-ci.org/m-labs/smoltcp/builds/423248510?utm_source=github_status&utm_medium=notification)

02:09 <benreynwar> Hi there!

02:09 <benreynwar> I'm taking a look at migen and was wondering whether it's possible to run migen tests against Verilator?

02:32 <cr1901_modern> benreynwar: Not at present. The migen simulator used to (till late 2015) call out to iverilog via VPI (so in theory Verilator support could be added); this approach had problems and was abandoned in favor of a Python-based homegrown simulator.

02:33 <cr1901_modern> benreynwar: Of course, nothing stops you from generating the Verilog and writing a testbench yourself :)

02:34 <benreynwar> @cr1901_modern: Yeah, but it would be cool to hook the migen tests up to Verilator. What were the issues with interacting with iverilog over VPI?

02:35 <cr1901_modern> No multiple clock domain support was the big one

02:35 <benreynwar> @cr1901_modern: I've only been playing with toy designs so far where the simulation speed isn't an issue, but I'd assume that the python simulator becomes limiting for large designs.

02:38 <benreynwar> @cr1901_modern: Is interfacing with Verilator something that there's interest in, or does the python simulator work well enough for most purposes?

02:39 <cr1901_modern> The latter, afaik. Perhaps talk to sb0 or rjo about this more

02:40 <cr1901_modern> There is legitimate reason to want to interface the Python simulator to Verilog code, but there are nontrivial impl issues that I've since forgotten.

02:42 <benreynwar> Cool. Thanks for the info.

14:24 <tpw_rules> sb0: i remember a couple months ago i told you i would totally come back with a new design for migen based on some ideas we had talked about. then i got busy. has there been any development of that between then and now?

14:25 <sb0> tpw_rules: no, there hasn't

14:25 <tpw_rules> are the ideas still something you're interested in working on?

14:28 <tpw_rules> or would you prefer to re-discuss? I'm back working in verilog and being unhappy with it

14:42 <tpw_rules> sb0: ^ ?

14:47 <sb0> still interested, but no time

14:50 <tpw_rules> is it okay if i work on it then? i could work on a spec for you to review, but maybe also an implementation

15:14 <sb0> sure

15:15 <GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to switching: https://github.com/m-labs/artiq/compare/4f963e1e1149...078c862618d2

15:15 <GitHub-m-labs> artiq/switching 078c862 Sebastien Bourdeauducq: drtio: add repeater (WIP, write only)

15:15 <GitHub-m-labs> artiq/switching 6057cb7 Sebastien Bourdeauducq: drtio: reorganize tests

15:33 <key2> tpw_rules: is you ridea private ?

15:35 <tpw_rules> key2: no, it's just i didn't want to re-explain it

15:35 <tpw_rules> i want a general overhaul of how signals work, using context managers and properties to do it

15:36 <tpw_rules> and to restructure the division between comb and sync

15:36 <key2> mmh

15:37 <tpw_rules> did you have any input or want to be involved

15:37 <tpw_rules> but basically like FHDL2

20:40 <mithro> benreynwar: Florent uses verilator to simulate full SoCs in his LiteX stuff

20:41 <mithro> benreynwar: But that is more about having an interactive system rather than testbench type stuff...

23:17 <benreynwar> mithro: Yep I saw that. pymtl generates cython wrappers for the verilated modules, so that it can run it's python tests. It's seems like it wouldn't be too complicated to apply the same technique to migen, but presumably there's a subtlety that I'm missing.

23:22 <mithro> benreynwar: btw are you in the #timvideos channel?

23:38 <benreynwar> mithro: I am now!