14:42 <GitHub-m-labs> [artiq] hartytp commented on issue #1155: - using the current standalone build... https://github.com/m-labs/artiq/issues/1155#issuecomment-424371735

15:08 <GitHub-m-labs> [artiq] hartytp commented on issue #1155: Running the same thing on the master build (125MHz f_rtio) I do see variation in the latency across power cycles. https://github.com/m-labs/artiq/issues/1155#issuecomment-424382390

15:36 <GitHub-m-labs> [artiq] hartytp commented on issue #1155: @sbourdeauducq maybe a silly thought, but AFAICT, the startup sequence for the master is:... https://github.com/m-labs/artiq/issues/1155#issuecomment-424393193

15:44 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1155: Quite possibly. Try adding some delay (spin_us) and see what happens, though the proper fix will be to wait for that pll to lock. https://github.com/m-labs/artiq/issues/1155#issuecomment-424396230

15:53 <marmelada> hey

15:53 <marmelada> Joe asked me to synchronize two saymas

15:53 <marmelada> is sayma master-slave working or do I need to use kasli sawg master?

15:53 <marmelada> @sb0?

15:56 <GitHub-m-labs> [artiq] hartytp commented on issue #1155: already building that :) https://github.com/m-labs/artiq/issues/1155#issuecomment-424400718

15:58 <hartytp> marmelada: synchronise the RF between two Saymas?

15:58 <hartytp> that doesn't work. Joe should know that

15:59 <hartytp> that's why we're working on the new synchronization mechanism...

15:59 <marmelada> even with kasli as sawg master?

16:00 <marmelada> I mean, even with random phases on boot he was under impression that we could work around that by adding delays

16:00 <hartytp> synchronisation between local rtio events and rf does not work

16:00 <marmelada> :(

16:00 <hartytp> well, if the phase is random at boot then it's not synchronized

16:01 <GitHub-m-labs> [artiq] hartytp commented on issue #1155: I need to run now, but provisionally it looks like a 1s delay there fixes this issue. I'll check more carefully later on. If it works, i'll submit a PR for a proper fix. https://github.com/m-labs/artiq/issues/1155#issuecomment-424402817

16:02 <hartytp> if you just want DRTIO Sayma slave with random phases at boot then, yes I think that worked (although I wouldn't call it synchronized)

16:02 <hartytp> sb0 would need to confirm though

16:02 <hartytp> as I haven't tried

16:03 <marmelada> ok, we can calibrate phases manually for now

16:41 <GitHub-m-labs> [artiq] jordens opened issue #1157: urukul: support low frequency (10 MHz) ref clock https://github.com/m-labs/artiq/issues/1157

18:20 <GitHub-m-labs> [artiq] hartytp opened pull request #1158: Kasli DRTIO master: do not init rtio core until serdes PLL has locked. (master...master) https://github.com/m-labs/artiq/pull/1158

19:11 <hartytp> bb-m-labs: force build --branch=pull/1158/merge artiq

19:11 <bb-m-labs> build forced [ETA 1h02m22s]

19:11 <bb-m-labs> I'll give a shout when the build finishes

19:14 <hartytp> bb-m-labs: force build --branch=pull/1158/merge artiq-board

19:14 <bb-m-labs> build forced [ETA 17m59s]

19:14 <bb-m-labs> I'll give a shout when the build finishes

19:15 <bb-m-labs> build #1871 of artiq-board is complete: Exception [exception conda_build_output] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1871

19:28 <GitHub-m-labs> [artiq] hartytp commented on issue #1158: NB this will break any DRTIO masters which don't have an RTIO clock multiplier with a `pll_locked` CSR ( just Sayma master AFACIT). @sbourdeauducq do you want me to add a config option, something like `HAS_RTIO_MUL` to feature gate the new firmware? https://github.com/m-labs/artiq/pull/1158#issuecomment-424470992

19:44 <bb-m-labs> build #1872 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1872

19:58 <GitHub-m-labs> [artiq] jordens commented on issue #1158: Not right now. In a couple of days. https://github.com/m-labs/artiq/pull/1158#issuecomment-424480255

20:04 <bb-m-labs> build #1873 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1873

20:08 <bb-m-labs> build #2612 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2612

20:09 <GitHub-m-labs> [artiq] hartytp commented on issue #1158: @jordens thanks, there is no particular hurry for this as far as I'm concerned. Just something I was looking at while doing acceptance testing for drtio switching. https://github.com/m-labs/artiq/pull/1158#issuecomment-424483790

21:58 <GitHub-m-labs> [artiq] hartytp commented on issue #1057: @sbourdeauducq I tried building a DRTIO master (master, not switching) with a 16-channel SUServo and found some quite large timing violations. ... https://github.com/m-labs/artiq/issues/1057#issuecomment-424515701

21:58 <GitHub-m-labs> [artiq] hartytp commented on issue #1057: @sbourdeauducq I tried building a DRTIO master (master, not switching) with an 8-channel SUServo and found some quite large timing violations. ... https://github.com/m-labs/artiq/issues/1057#issuecomment-424515701