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<shuffle2> is it possible to use run_simulation on a design using Tristate?
<shuffle2> (my naive code results in ValueError: ('Could not lower all specials', {<migen.fhdl.specials.Tristate...)
<sb0> shuffle2: not supported, you can implement it or isolate the tristate from the part you are simulating
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to switching: https://github.com/m-labs/artiq/commit/fa872c33414f0b758a46c356de7069adf7aa8b1c
<GitHub-m-labs> artiq/switching fa872c3 Sebastien Bourdeauducq: firmware: implement DRTIO destination survey
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<cr1901_modern> shuffle2: See the misoc cores/spi.py testbench for an example of how to emulate tristates in simulation
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<GitHub-m-labs> [artiq] sbourdeauducq pushed 3 new commits to switching: https://github.com/m-labs/artiq/compare/fa872c33414f...1ef39a98a7ae
<GitHub-m-labs> artiq/switching 1ef39a9 Sebastien Bourdeauducq: drtio: implement per-destination buffer space
<GitHub-m-labs> artiq/switching e95638e Sebastien Bourdeauducq: style
<GitHub-m-labs> artiq/switching 042b006 Sebastien Bourdeauducq: runtime: print destination up message for local RTIO
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<GitHub-m-labs> [artiq] cjbe opened issue #1150: ConnectionResetError on TCP Keepalive https://github.com/m-labs/artiq/issues/1150
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<GitHub-m-labs> [artiq] cjbe commented on issue #1150: It looks like the ARP cache is statically allocated at 8 entries long - is there any reason not to allocate this on the heap? https://github.com/m-labs/artiq/issues/1150#issuecomment-420992961
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<GitHub-m-labs> [artiq] whitequark commented on issue #1150: No, we can easily enlarge the ARP cache by a large factor. https://github.com/m-labs/artiq/issues/1150#issuecomment-421101945
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