00:10 <bb-m-labs> build #1800 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1800

00:13 <bb-m-labs> build #2577 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2577

01:09 <sb0> whitequark: great! thanks.

01:53 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #319: > If it is better,... https://github.com/m-labs/artiq/pull/319#issuecomment-412389525

04:13 <GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to nix: https://github.com/m-labs/artiq/commit/34329cf3665728c198beef65b98432ecaf6c70eb

04:13 <GitHub-m-labs> artiq/nix 34329cf Sebastien Bourdeauducq: artiq_flash: target Kasli by default

04:13 <GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/c172ec6de9e436d3dcc5758880d8cda2484c0450

04:13 <GitHub-m-labs> artiq/master c172ec6 Sebastien Bourdeauducq: artiq_flash: target Kasli by default

04:49 <bb-m-labs> build #1801 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1801

04:57 <GitHub177> [smoltcp] jhwgh1968 commented on issue #253: I am able to reproduce the problem, @pothos. It seems the socket does not send data with 524288, but does with 524287.... https://github.com/m-labs/smoltcp/pull/253#issuecomment-412408466

05:10 <bb-m-labs> build #1802 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1802

05:14 <bb-m-labs> build #2578 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2578

05:56 <GitHub-m-labs> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/5fe1bfe72a1cca8de3147b0f51ae324ec72e77d5

05:56 <GitHub-m-labs> migen/master 5fe1bfe William D. Jones: build/platforms: Add tinyfpga_a platform. (#111)

06:01 <bb-m-labs> build #305 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/305

08:50 <GitHub-m-labs> [artiq] marmeladapk commented on issue #319: > It reportedly works with the Linux subsystem for Windows, but I have not tried it.... https://github.com/m-labs/artiq/pull/319#issuecomment-412450386

09:49 <GitHub-m-labs> [artiq] sjmackenzie opened pull request #1132: nix: separated buildtime & runtime dependencies (nix...nix) https://github.com/m-labs/artiq/pull/1132

10:31 <GitHub-m-labs> [artiq] sbourdeauducq closed pull request #1132: nix: separated buildtime & runtime dependencies (nix...nix) https://github.com/m-labs/artiq/pull/1132

10:44 <GitHub-m-labs> [artiq] sjmackenzie commented on issue #1132: Once (if) you've updated all the code you should remove this [line](https://github.com/m-labs/artiq/pull/1132/files#diff-4d842add0dac68884b9567d925f39b66R125). This'll run your tests automatically upon building of every `artiq` derivation, for now it fails. https://github.com/m-labs/artiq/pull/1132#issuecomment-412478592

10:45 <GitHub-m-labs> [artiq] sjmackenzie commented on issue #1132: Once (if) you've updated all the nix code you should remove this [line](https://github.com/m-labs/artiq/pull/1132/files#diff-4d842add0dac68884b9567d925f39b66R125). This'll run your tests automatically upon building of every `artiq` derivation, for now it fails. https://github.com/m-labs/artiq/pull/1132#issuecomment-412478592

10:46 <GitHub-m-labs> [artiq] sjmackenzie commented on issue #1132: Once (if) you've updated all the nix code you should remove this [line](https://github.com/m-labs/artiq/blob/nix/nix/artiq.nix#L125). This'll run your tests automatically upon building of every `artiq` derivation, for now it fails. https://github.com/m-labs/artiq/pull/1132#issuecomment-412478592

12:36 <marmelada> hey, sb0

12:36 <marmelada> you wanted calibration log

12:37 <marmelada> oh, nvm

12:41 <marmelada> well, I cancel that nvm

12:41 <marmelada> I still have 180 deg phase on the same allaki

12:42 <marmelada> using matched cables

12:46 <GitHub141> [smoltcp] pothos commented on issue #253: @jhwgh1968 I think e.g. for the tap interface setup as mentioned in the README it should be... https://github.com/m-labs/smoltcp/pull/253#issuecomment-412505588

13:01 <marmelada> sb0: here's the log you requested https://hastebin.com/cemizozomu.rb

13:18 <marmelada> oh, I found the cause

13:39 <marmelada> https://github.com/sinara-hw/sinara/issues/581

13:40 <marmelada> how come nobody noticed it?

14:15 <sb0> marmelada: okay that log looks good

14:16 <sb0> what values did it give you for sysref_phase_fpga and sysref_phase_dac?

14:16 <sb0> that's not the calibration log, that's a log using the results of a previous calibration

14:37 <sb0> marmelada: what about the sysrefs on the scope?

15:13 <marmelada> haven't checked them yet

16:05 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #319: Things don't look too good with WSL at the moment. Setting things up requires many steps, and nix tickles some WSL bug that need working around - these two problems might get better as there are plans to add NixOS to the MS Store. A bigger problem is the GUI; this needs yet another step to manually install and start a X server on the native Windows side. Then it is

17:37 <marmelada> sb0: when using master I have phase between dac0 and dac1 dependent on frequency set

18:15 <GitHub-m-labs> [artiq] klickverbot commented on issue #319: Also note that WSL isn't even supported on all current Windows 10 builds – for example, it hasn't hit whatever enterprise fork our university is mandating (even on machines where we otherwise have full admin access), as I was dismayed to find out a while back. https://github.com/m-labs/artiq/pull/319#issuecomment-412613831

18:53 <marmelada> on another board (which also has phase between dacs change when frequency changes): [ 13.524662s] INFO(board_artiq::jesd204sync): calibrating SYSREF phase offse t at FPGA... [ 13.542312s] INFO(board_artiq::jesd204sync): ...done, phase offset: 132 [ 13.552550s] INFO(board_artiq::jesd204sync): aligning SYSREF with RTIO... [ 13.578576s] INFO(board_artiq::jesd204sync): ...done (64/64 slips) [ 13.586748s] INFO(b

23:11 <cr1901_modern> Well this is good... I have a todoist bullet: "Arty S7 spiflash clk fix" under "Migen PR List". I have no idea what that's referring to.

23:29 <cr1901_modern> https://github.com/enjoy-digital/arty-soc/blob/dcaea692fd2ff0a689489da9a2b4acec6eb5c403/arty_base.py#L185-L189 Hmm I guess it's not a bug that the signal's absent

23:29 <cr1901_modern> clk signal*

23:32 <cr1901_modern> Okay, so AIUI, for all 7-series Xilinx FPGAs, you don't actually have access to the SPI flash clk, but you need to instantiate a STARTUPE2?

23:32 <cr1901_modern> SPI flash clk pin*