SKYWARN has quit [Remote host closed the connection]
d_n|a_ has quit [*.net *.split]
Gurty has quit [*.net *.split]
ohsix has quit [*.net *.split]
ronyrus has quit [*.net *.split]
acathla has quit [*.net *.split]
ronyrus has joined #m-labs
cr1901_modern1 has joined #m-labs
d_n|a_ has joined #m-labs
Gurty has joined #m-labs
acathla has joined #m-labs
ohsix has joined #m-labs
cr1901_modern has quit [Ping timeout: 272 seconds]
cr1901_modern1 has quit [Quit: Leaving.]
cr1901_modern has joined #m-labs
liguo has joined #m-labs
liguo has quit [Remote host closed the connection]
<sb0>
marmelada: please give more details: what frequencies, what phases, how you program the SAWG (kernel source), how you load the kernel, how you measure the phases
<sb0>
marmelada: that's the log for the fpga sysref, what is the one for the dac sysref?
Laif has joined #m-labs
mcintosh12 has joined #m-labs
mcintosh12 has quit [Remote host closed the connection]
<marmelada>
I program SAWG using sines.py from examples with artiq_run
<marmelada>
I only changed frequency
<marmelada>
I checked, that changing delay doesn't affect phase
<marmelada>
I have some screenshots from oscilloscope, perhaps I should open an issue?
nukedclx1 has joined #m-labs
nukedclx1 has quit [Remote host closed the connection]
jfng[m] is now known as jfng
X-Scale has joined #m-labs
DenSchub15 has joined #m-labs
DenSchub15 has quit [Remote host closed the connection]
Phex has joined #m-labs
PlasmaStar18 has joined #m-labs
PlasmaStar18 has quit [Remote host closed the connection]
Phex has quit [Remote host closed the connection]
RyanKnack26 has joined #m-labs
RyanKnack26 has quit [Remote host closed the connection]
<GitHub-m-labs>
[artiq] jordens commented on issue #1114: Does that really work? It should suffer from the same semantics problem and I remember seeing a proper error for that. You can't both get and set a dataset in the same experiment. https://github.com/m-labs/artiq/issues/1114#issuecomment-412851966
<GitHub-m-labs>
artiq/master 2463e56 David Nadlinger: compiler: Fix attribute writeback with skipped fields...
<d_n|a>
whitequark: How is attribute writeback tested? I wanted to add a regression test for ^, but didn't see anything – your fix for #1088 didn't have any actual writeback tests either
<d_n|a>
sb0: (How) is satman tested on the m-labs buildbot?
<whitequark>
d_n|a: I thought it was tested in test_embedding.py, but looks like it isn't
<whitequark>
d_n|a: satman isn't tested
<rjo>
key2: pong
<key2>
rjo: as you did the jtag proxy, you probably could help. I made my own jtag tap and interfaced it with the tdi/tck/tdo/tms of the BSCANE2
<key2>
rjo: putting p_JTAG_CHAIN = 1
<key2>
now I am trying to see it with openocd
<key2>
what am I supposed to do in order to get the BSCANE2 to shift into my tdi
<key2>
do I have to play with the USER1 of the fpga ?
<rjo>
key2: bscane2 only uses the td? driven by your code when IR=USER1. i.e. your logic is redundant/irrelevant in that sense. but you can feed out your driven td? on a different pin and look at that with your jtag adapter.
Guest18247 has joined #m-labs
Guest18247 has quit [Remote host closed the connection]
<key2>
rjo: but if I have a TAP that I want to connect either to 4 IO of the fpga, or chain internally to the TAP of the xilinx, what is the solution ?
naos7 has quit [Remote host closed the connection]
<rjo>
key2: in the first case there is no problem. just do it. in the second case, since bscane2 doesn't give you "its" tdo, you are out of luck unless you bridge tdo to your core outside the fpga.
<rjo>
if you want your core to be a tap behind the fpga, you need access to the fpga's tdo (connect it to your core's tdi). if you want to be ahead of the fpga, you need to connect your tdo to the fpga's tdi. in either case that needs to be done outside the fpga.
<sb0>
marmelada: ok and please post the exact source and descriptions of expected and actual waveforms
zhongfu8 has joined #m-labs
zhongfu8 has quit [K-Lined]
<key2>
rjo: that's what I wanted to know
<key2>
rjo: so the other option is to use USER1-4
<key2>
which ends up being a generated TDO, right ?
<rjo>
key2: yes. bscane2 give you "one DR" each within the fpga tap. and the fpga tap takes care of muxing the DR TDOs.
<key2>
I see
<sb0>
marmelada: any progress with SYSREF measurements?
<GitHub-m-labs>
[artiq] jordens commented on issue #1114: Reproducibility and data provenience. The typical way to implement this is to have one experiment that evolves data with `x=get_dataset("x_ref"); ...; {set,mutate}_dataset("x", ...)` and another that "commits" by doing `set_dataset("x_ref", get_dataset("x")`. https://github.com/m-labs/artiq/issues/1114#issuecomment-412937064
RichiH23 has quit [Remote host closed the connection]
<GitHub-m-labs>
[artiq] marmeladapk commented on issue #1133: @hartytp Changing delay doesn't affect phase difference (I measured phase, changed delay and frequency, changed frequency once again and measured phase to make sure that frequency was changed). https://github.com/m-labs/artiq/issues/1133#issuecomment-412966085
<GitHub-m-labs>
[artiq] jordens commented on issue #1133: @marmeladapk I don't see the correlation between your description and the screenshots. The phases in the screenshots are all different (see the measurements window). If you look at ... https://github.com/m-labs/artiq/issues/1133#issuecomment-412983426
drot11 has joined #m-labs
drot11 has quit [Remote host closed the connection]
woddf26 has joined #m-labs
woddf26 has quit [Killed (Unit193 (Spam is not permitted on freenode.))]
IntPtr2 has joined #m-labs
IntPtr2 has quit [Remote host closed the connection]