<harty>
context: I'm using sync_struct in another project and this gives a lot of noise
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<iofs_CUI>
Hi, I'm using urukul AD9910 and I was trying to set the ref_clk to 10 MHz
<iofs_CUI>
But I found that it seems there is a cpld fanout divideron this board
<iofs_CUI>
which divider the input cpld_ref_clk by 4
<GitHub-m-labs>
[artiq] whitequark closed issue #1088: compiler asserts trying to emit attribute writeback for function pointer lists https://github.com/m-labs/artiq/issues/1088
<iofs_CUI>
Since at least AD9910 needs 370 MHz after the PLL, and the the PLL_n cannot be larger than 127, this makes the ref_clk must larger than abouht 14 MHz
<iofs_CUI>
So why do we need this "clock fanout divider"? Can we disable this?
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<rjo>
harty: ECONNRESET is an unclean reset by the remote side. why ignore that?
<rjo>
iofs_CUI: that's set by the cpld. you'll need to change that code.
<rjo>
iofs_CUI: it's needed because the dominant use cases 100 MHz and 125 MHz are too high for the AD9910 PFD.
<iofs_CUI>
I didn't find it in urukul.py . Can you give me a clue about how to change this code?
<iofs_CUI>
And, about the AD9912 board, there is no such divider in the code. But 10 MHz ref_clk just could not work
<iofs_CUI>
20 MHz ref_clk works well for AD9912.
<iofs_CUI>
Any suggetion for this?
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<harty>
rjo: okay, maybe I'm thinking about this the wrong way, but it seems that by the time we get to close() we often don't care if the remote has already closed the connection
<rjo>
harty: afaict ECONNRESET is a RST that preceeds a FIN from any side. seeing that is not ok.
<rjo>
also not in the close method.
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<rjo>
if you are not doing anything with a connection and you get an unexpected reset, then hours later you decide to close() it, afaict this is the place where the exception would surface.
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<harty>
rjo: ack
<harty>
fine, I'll have a look at my server code and check that I'm closing all connections correctly
<marmelada>
I kind of understand your hatred towards xilinx now ;)
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<marmelada>
sb0: I deleted sysref_phase_dac and sysref_phase_fpga configuration keys with artiq_coremgmt config remove sysref_phase_dac sysref_phase_fpga
<marmelada>
and I still get " failed to align SYSREF at DAC: SYSREF margins a t DAC are too small, board needs recalibration"
<marmelada>
it's most likely something with board, right?
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<marmelada>
sb0: should there be a 180 deg phase difference on two allaki outputs?
<marmelada>
same allaki
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