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<GitHub-m-labs> [artiq] sbourdeauducq closed issue #1080: Sayma PRBS errors when FPGA JESD transceiver clock is GTP_CLK2 https://github.com/m-labs/artiq/issues/1080
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1129: @marmeladapk Any progress with measuring SYSREF?... https://github.com/m-labs/artiq/issues/1129#issuecomment-413729129
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<GitHub-m-labs> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/2d37c7807375c107a12d6e397dd968d66c81989e
<GitHub-m-labs> migen/master 2d37c78 Robin Ole Heinemann: add indexed part select support
<bb-m-labs> build #306 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/306
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<GitHub-m-labs> [artiq] sbourdeauducq pushed 3 new commits to nix: https://github.com/m-labs/artiq/compare/2c55f2ce4b2e...233c841f2e9e
<GitHub-m-labs> artiq/nix 233c841 Sebastien Bourdeauducq: nix: remove bogus version string
<GitHub-m-labs> artiq/nix 3d332cc Sebastien Bourdeauducq: nix: update README
<GitHub-m-labs> artiq/nix 4155853 Sebastien Bourdeauducq: nix: add Clang back
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to nix: https://github.com/m-labs/artiq/commit/e978430c54dc1ec400d89ee2b26f53fcb6921075
<GitHub-m-labs> artiq/nix e978430 Sebastien Bourdeauducq: nix: add warnings to README
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to nix: https://github.com/m-labs/artiq/commit/341437ea5007248c96e962396df3459d337711c0
<GitHub-m-labs> artiq/nix 341437e Sebastien Bourdeauducq: nix: remove outputcheck and lit
<GitHub-m-labs> [artiq] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/artiq/compare/2463e5667d1b...66e33a66d673
<GitHub-m-labs> artiq/master 66e33a6 Sebastien Bourdeauducq: test: enable TTL loopback tests on Kasli
<GitHub-m-labs> artiq/master d707d2f Sebastien Bourdeauducq: test: relax TTL timing requirements to support DIO EEM
<GitHub-m-labs> artiq/master 1ba12e1 Sebastien Bourdeauducq: gui/log: print messages in tooltips...
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1004: TTL in and out done. https://github.com/m-labs/artiq/issues/1004#issuecomment-413762728
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<bb-m-labs> build #1805 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1805
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<bb-m-labs> build #1806 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1806
<bb-m-labs> build #2580 of artiq is complete: Exception [exception board_unlock_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2580 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1127: @enjoy-digital I see no clock domain crossing structure (e.g. ``MultiReg``) between the CSRs ``enable``, ``ready``, ``prbs_config``, and ``stpl_enable`` which are in the ``sys`` domain, and their corresponding signals in ``JESD204BCoreTX`` which are in the ``jesd`` domain. Or am I missing out something? https://github.com/m-labs/artiq/issues/1127#issuecomment-
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1127: Since with the current way the code is organized, the clock domain renaming for ``JESD204BCoreTX`` is outside the core and you do not know what the domain name is in ``JESD204BCoreTXControl``. Is that why you omitted the CDC on those signals? https://github.com/m-labs/artiq/issues/1127#issuecomment-413818607
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1127: Since with the current way the code is organized, the clock domain renaming for ``JESD204BCoreTX`` is outside the core and you do not know what the domain name is in ``JESD204BCoreTXControl``. Is that why you omitted the CDC on those signals? https://github.com/m-labs/artiq/issues/1127#issuecomment-413818607
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #1127: The way it's coded, JESD204BCoreTX expects these signals in sys clk domain:... https://github.com/m-labs/artiq/issues/1127#issuecomment-413824471
<GitHub-m-labs> [artiq] hartytp commented on issue #1129: @sbourdeauducq nope, I don't have it yet. FYI: I'm away next week, so the earliest I can look at this now is the 27th, assuming I get the hardware back by then. https://github.com/m-labs/artiq/issues/1129#issuecomment-413825896
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1127: > ready is resynchronizer with a Multireg in JESD204BCoreTX.... https://github.com/m-labs/artiq/issues/1127#issuecomment-413826027
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1127: > Resynchronized into the jesd domain, so, that doesn't work.... https://github.com/m-labs/artiq/issues/1127#issuecomment-413826569
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<GitHub-m-labs> [artiq] enjoy-digital commented on issue #1127: The way it's coded, JESD204BCoreTX expects these signals in sys clk domain:... https://github.com/m-labs/artiq/issues/1127#issuecomment-413824471
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<GitHub-m-labs> [artiq] enjoy-digital commented on issue #1127: OK, thanks for the review. (i wouldn't have catched this without a second pair or eyes)... https://github.com/m-labs/artiq/issues/1127#issuecomment-413832908
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1004: > Freq gen (port)... https://github.com/m-labs/artiq/issues/1004#issuecomment-413871803
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<sb0> 126 sayma restarts with dac sync and zero bug...
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<hartytp> sb0: really? that's great!
<hartytp> so, were all the remaining sync issues related to JESD, not the 7043?
<sb0> dac sync == sync between the DACs
<hartytp> aah k
<hartytp> still, that's good progress
<sb0> i.e. with the DAC/RTIO sync that does the problematic 7043 slips disabled
<sb0> i've implemented external clocking for drtio too, testing now ...
<hartytp> nice thanks!
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<sb0> seems to work
<sb0> so really now #1129 (7043 cycle slip issue) is the main problem
<hartytp> sb0: did the new changes fix https://github.com/m-labs/jesd204b/issues/12
<sb0> still waiting on a compilation for that
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<sb0> bb-m-labs: force build --props=package=jesd204b conda-lin64
<bb-m-labs> build forced [ETA 8m44s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> bb-m-labs: stop build conda-lin64 push
<bb-m-labs> build 418 interrupted
<bb-m-labs> build #418 of conda-lin64 is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/418
<GitHub> [conda-recipes] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/conda-recipes/commit/e815690b9a8c43fcf4b025a8cd454ecaedae32c1
<GitHub> conda-recipes/master e815690 Sebastien Bourdeauducq: jesd204: bump
<sb0> bb-m-labs: force build --props=package=jesd204b conda-lin64
<bb-m-labs> build forced [ETA 8m44s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #419 of conda-lin64 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/419
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<sb0> hartytp, I think https://github.com/m-labs/jesd204b/issues/12 is a separate issue, and it doesn't print anything in the board log
<sb0> _florent_: right?
<sb0> hartytp, what you were talking about is probably https://github.com/m-labs/artiq/issues/727 and yes, it seems resolved :)
<_florent_> sb0: i think that's the same issue
<sb0> _florent_: aren't those "sync" requests handled by the gateware and invisible?
<_florent_> sb0: ah yes, then you can eventually pring the "restart_count" register
<_florent_> print
<GitHub-m-labs> [artiq] sbourdeauducq closed issue #1127: Sayma intermittent STPL test failure https://github.com/m-labs/artiq/issues/1127
<GitHub-m-labs> [artiq] hartytp commented on issue #727: nice! https://github.com/m-labs/artiq/issues/727#issuecomment-413893308
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<hartytp> sb0: I wondered whether both issues had the same cause
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<bb-m-labs> build #1807 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1807
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<GitHub-m-labs> [artiq] sbourdeauducq reopened issue #1127: Sayma intermittent STPL test failure https://github.com/m-labs/artiq/issues/1127
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #727: This bug seems gone for good, all DAC inits worked the first time in 87 reboots. https://github.com/m-labs/artiq/issues/727#issuecomment-413905518
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1115: @klickverbot Can you finish this before 4.0? (Which should be soon and mostly depends on https://github.com/m-labs/artiq/issues/1007) https://github.com/m-labs/artiq/pull/1115#issuecomment-413909786
<bb-m-labs> build #1808 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1808
<bb-m-labs> build #2581 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2581
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<GitHub-m-labs> [artiq] prasath-d opened issue #1135: Text missing on right click context menu in linux https://github.com/m-labs/artiq/issues/1135
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