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GitHub-m-labs >
migen/master 2d37c78 Robin Ole Heinemann: add indexed part select support
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GitHub-m-labs >
artiq/nix 233c841 Sebastien Bourdeauducq: nix: remove bogus version string
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GitHub-m-labs >
artiq/nix 3d332cc Sebastien Bourdeauducq: nix: update README
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GitHub-m-labs >
artiq/nix 4155853 Sebastien Bourdeauducq: nix: add Clang back
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GitHub-m-labs >
artiq/nix e978430 Sebastien Bourdeauducq: nix: add warnings to README
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GitHub-m-labs >
artiq/nix 341437e Sebastien Bourdeauducq: nix: remove outputcheck and lit
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GitHub-m-labs >
artiq/master 66e33a6 Sebastien Bourdeauducq: test: enable TTL loopback tests on Kasli
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GitHub-m-labs >
artiq/master d707d2f Sebastien Bourdeauducq: test: relax TTL timing requirements to support DIO EEM
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GitHub-m-labs >
artiq/master 1ba12e1 Sebastien Bourdeauducq: gui/log: print messages in tooltips...
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GitHub-m-labs >
[artiq] sbourdeauducq commented on issue #1127: @enjoy-digital I see no clock domain crossing structure (e.g. ``MultiReg``) between the CSRs ``enable``, ``ready``, ``prbs_config``, and ``stpl_enable`` which are in the ``sys`` domain, and their corresponding signals in ``JESD204BCoreTX`` which are in the ``jesd`` domain. Or am I missing out something?
https://github.com/m-labs/artiq/issues/1127#issuecomment-
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GitHub-m-labs >
[artiq] sbourdeauducq commented on issue #1127: Since with the current way the code is organized, the clock domain renaming for ``JESD204BCoreTX`` is outside the core and you do not know what the domain name is in ``JESD204BCoreTXControl``. Is that why you omitted the CDC on those signals?
https://github.com/m-labs/artiq/issues/1127#issuecomment-413818607
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GitHub-m-labs >
[artiq] sbourdeauducq commented on issue #1127: Since with the current way the code is organized, the clock domain renaming for ``JESD204BCoreTX`` is outside the core and you do not know what the domain name is in ``JESD204BCoreTXControl``. Is that why you omitted the CDC on those signals?
https://github.com/m-labs/artiq/issues/1127#issuecomment-413818607
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sb0 >
126 sayma restarts with dac sync and zero bug...
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hartytp >
sb0: really? that's great!
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hartytp >
so, were all the remaining sync issues related to JESD, not the 7043?
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sb0 >
dac sync == sync between the DACs
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hartytp >
still, that's good progress
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sb0 >
i.e. with the DAC/RTIO sync that does the problematic 7043 slips disabled
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sb0 >
i've implemented external clocking for drtio too, testing now ...
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hartytp >
nice thanks!
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sb0 >
seems to work
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sb0 >
so really now #1129 (7043 cycle slip issue) is the main problem
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sb0 >
still waiting on a compilation for that
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sb0 >
bb-m-labs: force build --props=package=jesd204b conda-lin64
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bb-m-labs >
build forced [ETA 8m44s]
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bb-m-labs >
I'll give a shout when the build finishes
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sb0 >
bb-m-labs: stop build conda-lin64 push
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bb-m-labs >
build 418 interrupted
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GitHub >
conda-recipes/master e815690 Sebastien Bourdeauducq: jesd204: bump
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sb0 >
bb-m-labs: force build --props=package=jesd204b conda-lin64
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bb-m-labs >
build forced [ETA 8m44s]
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bb-m-labs >
I'll give a shout when the build finishes
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sb0 >
_florent_: right?
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_florent_ >
sb0: i think that's the same issue
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sb0 >
_florent_: aren't those "sync" requests handled by the gateware and invisible?
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_florent_ >
sb0: ah yes, then you can eventually pring the "restart_count" register
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hartytp >
sb0: I wondered whether both issues had the same cause
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