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<GitHub7>
[smoltcp] pothos commented on issue #253: @jhwgh1968 In my tests it works well except for buffer sizes which lead to a situation where a socket can't connect. Your test value 262143 works, 524288 works not, 1000000 works, 1048576 does not etc… I haven't looked into detailed stocket state yet, but maybe you already have an idea?... https://github.com/m-labs/smoltcp/pull/253#issuecomment-410622137
<sb0>
larsc, do you know if the hmc7043 is glitchless when adjusting the digital delays?
<sb0>
(the 1/2 clkin delay)
<sb0>
the DAC sync sometimes craps out when I touch the digital delay (by an amount that should not do anything), so I suspect it isn't
<sb0>
it's remarkable how many bugs this chip can cause
<larsc>
I believe it is supposed to be glitchless
<larsc>
do you move the DAC clock or the SYSREF?
<sb0>
SYSREF
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<sb0>
when the breakage happens, I'm doing two things: resetting the analog fine delay to 0, and increasing the digital delay by 1/2 clkin
<sb0>
touching the analog delay alone doesn't seem to cause issues, so it would appear to be glitchless as advertised
<sb0>
though I haven't tried giving it large jumps without simultaneously changing the digital delay
<larsc>
if the sysref jumps from one clock cyclce to the next that might upset the DAC
<sb0>
yep, the DAC does report such a sysref jump
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<larsc>
but according to your calculations the increase in delay is not enough to cause such a jump?
<sb0>
yes
<sb0>
well
<sb0>
what I am doing is: setting the analog delay to 0, then immediately increasing the digital delay
<sb0>
if those actions are taken in sequence then that shouldn't cause a jump
<sb0>
if the analog delay has some response time and the adjustement doesn't complete before the digital delay is increased, there may be a problem
<sb0>
well. i guess a simple workaround is to tell the DAC to ignore SYSREF while the 7043 is doing its thing
<sb0>
so much for the "Glitchless phase control of signals" in the datasheet ...
<sb0>
at least the ad9154 seems to have working and thought-through sysref diagnostics
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<GitHub-m-labs>
artiq/master 65f198b Sebastien Bourdeauducq: kasli: use tester EEMs for DRTIO, add Urukul-Sayma sync example
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<GitHub195>
[smoltcp] pothos commented on issue #253: @jhwgh1968 In my tests it works well except for buffer sizes which lead to a situation where a socket can't connect. Your test value 262143 works, 524288 works not, 1000000 works, 1048576 does not etc… I haven't looked into detailed stocket state yet, but maybe you already have an idea?... https://github.com/m-labs/smoltcp/pull/253#issuecomment-410622137
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<GitHub44>
[smoltcp] pothos commented on issue #253: @jhwgh1968 In my tests it works well except for buffer sizes which lead to a situation where a socket can't connect. Your test value 262143 works, 524288 works not, 1000000 works, 1048576 does not etc… I haven't looked into detailed stocket state yet, but maybe you already have an idea?... https://github.com/m-labs/smoltcp/pull/253#issuecomment-410622137
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<hartytp>
sb0: IIRC the HMC7043 phase shifting really is glitchless
<hartytp>
I set Sayma up to scan the analog and digital delays at the same time and looked on a scope
<hartytp>
think I have a video somewhere
<sb0>
hartytp, yes, but you can't change both analog and digital delays at the same time in a glitchless manner
<hartytp>
true
<hartytp>
(anyway, that test was a while ago, so would need to dig out my notes to confirm that memory)
<sb0>
anyway, the latest code deals with that, and I don't see any error in the log anymore
<sb0>
though the DAC outputs are still borked
<sb0>
typical breakage is +53.32ns of delay or -53.32ns of delay
<sb0>
that's 8 cycles of the 150MHz clock
<sb0>
larsc, any idea what can cause DACs to have those jumps?
<sb0>
i.e. in most cases (i.e. unless some other shitbug hits), I measure the phase difference between the DACs to be 0 (which is what it should be), -8 cycles of 150MHz, or +8 cycles of 150MHz
<sb0>
what seems to be the problem, on the other hand, is either the DAC or the 7043 has some history of previous SYSREF settings
<sb0>
set sysref phases to known-good values, initialize everything once => DAC are synchronized properly
<sb0>
mess around with sysref, then program the same SYSREF phase value and resynchronize the DAC => intermittent 0/-8/+8 bug above
<sb0>
hartytp, when you have time, can you measure with the fast scope that the final SYSREF phases with scenario #2 are indeed what they are supposed to be?
<sb0>
well I can try to narrow it down further in code first...
<sb0>
but at least we have a workaround, and relatively stable SAWG with 8 channels now.
<sb0>
also, any sights of the STPL bug? or is it only my board?
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<sb0>
okay, it's board_artiq::jesd204sync::sysref_auto_rtio_align that breaks DAC sync...
<sb0>
there are no DAC resyncs in that function, so probably that crappy 7043 is at it again
<sb0>
hartytp, had you tested the 7043 slips on the scope? any quirks or misbehavior?
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<cr1901>
sb0: I updated tinyfpga_a platform PR with that 6 line change finally (took me long enough). Everything checks out on my end at least (though diamond support still needs work...)