<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #319: I've been giving Nixos a try, and I don't think it's fair to call nix a "naive hack". There is definitely a lot of thought that went into it. You can run a complete, usable Linux distro out of nix, and things actually work properly. The main issue I have with it is the lack of documentation, or documentation that has gone out of date.... https://github.com/m-la
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<whitequark>
bb-m-labs: force build --branch=rust-1.28 artiq
<bb-m-labs>
build forced [ETA 42m35s]
<bb-m-labs>
I'll give a shout when the build finishes
<GitHub-m-labs>
artiq/rust-1.28 1329af7 whitequark: firmware: migrate to Rust 1.28.0....
<kay2>
sb0: if I have a submodule foo that has a Signal bar, how can I get self.foo.bar generate a name "reg foo_bar" instead of "reg bar" ?
<kay2>
basically right now when I generate verilog, all the signals from my submodules are flat
<kay2>
so when looking in analyzer, it's a bit messy, i was wondering if there was a way to tell migen to generate them with the name of the submodules
<kay2>
prefixed
<sb0>
kay2, if you change the namer code (shouldn't be a complex change) yes
<kay2>
what do you mean to change the namer code ?
<sb0>
maybe add a feature that lets you mark certain modules as always being selected for naming
<whitequark>
the namer code is very much not easy to change.
<kay2>
what do you call thenamer code
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<sb0>
namer.py in migen
<sb0>
adding this "select module" feature shouldn't be very complicated afaict
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<kay2>
actually it does prefix automatically, it's just that if I do this: setattr(self.submodules, "mymod3", MySub(5))
<kay2>
it doesnt care about the "mymod3"
<kay2>
it would still use "mysub" instead
<sb0>
the problem here is that the tracer doesn't have a way to extract that string
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<kay2>
is there a way to force it in the MySub itself ?
<GitHub-m-labs>
[artiq] jordens commented on issue #319: Don't make a straman out of that comment. If it is better, if it works on Windows as well, it it leads to less maintenance, if it gives anywhere near the completeness of a Python distribution like conda, if it is well documented, and if it means an end to the complaining, I am clearly wrong.... https://github.com/m-labs/artiq/pull/319#issuecomment-412347617
<GitHub-m-labs>
[artiq] jordens commented on issue #319: Don't make a strawman out of that comment. If it is better, if it works on Windows as well, it it leads to less maintenance, if it gives anywhere near the completeness of a Python distribution like conda, if it is well documented, and if it means an end to the complaining, I am clearly wrong.... https://github.com/m-labs/artiq/pull/319#issuecomment-412347617
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<kay2>
sb0: and is there a way to tell the tracer to change the name of the module ?
<sb0>
kay2: not right now, but you can add it
<kay2>
how ?
<whitequark>
bb-m-labs: force build --branch=rust-1.28 artiq
<bb-m-labs>
build forced [ETA 42m35s]
<bb-m-labs>
I'll give a shout when the build finishes
<whitequark>
rjo: ok, nothing obviously wrong, let me clone and build that.
<rjo>
i tried to determine which factor of the dot product it builds that indirection for, and i am reasonably certain that it is the ADC_SAMPLES (a.k.a. "x") but i got a headache looking at IR, MIR and ASM trying to convince myself.
<whitequark>
rjo: in readme, you need to move `cargo install itm` after `rustup target add thumbv7m-none-eabi`
<whitequark>
oh hm, doesn't help, something else is broken
<rjo>
ack. it's also optional.
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<rjo>
whitequark: ah. thumbv7em-none-eabihf
<whitequark>
right, but it still doesn't work efven after that
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<whitequark>
bb-m-labs: retry
<whitequark>
bb-m-labs: force build --branch=rust-1.28 artiq
<bb-m-labs>
build forced [ETA 42m35s]
<bb-m-labs>
I'll give a shout when the build finishes
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<rjo>
whitequark: thanks. speaking generally, i had the impression that this was a rust or llvm trying to optimize the repeated iterations over the ADC_SAMPLES array. i just have no idea why and how it thinks that would help. the weird table that it generates goes away if i only run one FIR filter.
<GitHub-m-labs>
artiq/rust-1.28 5da45f9 whitequark: firmware: migrate to Rust 1.28.0....
<whitequark>
bb-m-labs: force build --branch=rust-1.28 artiq
<bb-m-labs>
build forced [ETA 42m35s]
<bb-m-labs>
I'll give a shout when the build finishes
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<vup>
hey, i added indexed-part support to migen (the "vector[offset+:length]" syntax), imo it makes the generated verilog code much easier to read than the alternative of shift and slice, is there any interest in adding that officially to migen? should i open a pull request to upstream this feature?
<bb-m-labs>
build #2576 of artiq is complete: Exception [exception python_unittest_2 board_unlock_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2576 blamelist: whitequark <whitequark@whitequark.org>
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