<sb0>
cr1901_modern, synthesis results should be the same, but separating the output behavior from the state transitions makes the code harder to read
<sb0>
omid, or you can read the FPGA gateware source
<cr1901_modern>
Ahh I didn't know the synth results were supposed to be the same. I'll have to test. Ack on the code readability (though your method generates more signals thanks to the need for "_ce").
<sb0>
the optimizers should handle them
<sb0>
one lab in china actually reproduced the whole nist hardware based on the source code and the pictures. when I visited them the first time I was greeted by several artiq screens with everything up and running...
<cr1901_modern>
This seems to be the fate of most open source gateware/hardware (though from pictures alone is pretty impressive)
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<_florent_>
sb0: i don't think i know enough to be able to help, i would need to have a close look
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<GitHub-m-labs>
[artiq] philipkent commented on issue #1097: We were able to build the target binaries by manually installing the artiq-dev package and specifying the version using: `conda create -n artiq-dev artiq-dev=3.6`. It looks like using the conda/artiq-dev.yaml file from the release-3 branch installs the 4.0 version of the artiq-dev package by default. https://github.com/m-labs/artiq/issues/1097#issuecomment-403
<cr1901_modern>
Gah I wanted to try to put a microcontroller core on icestick, and thought navre was the answer. But navre for some reason has an async GPR read port, and ice40 has no distributed RAM...
<cr1901_modern>
I can't seem to figure out why the read port is async, but the comments explicitly say GPRs use distributed RAM