sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/fe93a454d68b6e6db697c0c0c6f550ec95bbb691
<GitHub-m-labs> artiq/master fe93a45 Sebastien Bourdeauducq: fmcdio_vhdci_eem: fix direction shift register permutation and polarity
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #817: This works except for the FMC card line direction control.... https://github.com/m-labs/artiq/issues/817#issuecomment-406179120
<GitHub-m-labs> [artiq] gkasprow commented on issue #817: ... https://github.com/m-labs/artiq/issues/817#issuecomment-406181410
<GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/fe93a454d68b...d152506ecbf0
<GitHub-m-labs> artiq/master d152506 Sebastien Bourdeauducq: sayma: update fmcdio_vhdci_eem demo
<GitHub-m-labs> artiq/master 8dfcd46 Sebastien Bourdeauducq: fmcdio_vhdci_eem: naming consistency
<GitHub-m-labs> [artiq] sbourdeauducq closed issue #817: VHDCI for Sayma https://github.com/m-labs/artiq/issues/817
<bb-m-labs> build #1728 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1728
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<bb-m-labs> build #910 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/910
<bb-m-labs> build #2521 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2521
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<bb-m-labs> build #1729 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1729
<bb-m-labs> build #911 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/911
<bb-m-labs> build #2522 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2522
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1080: @gkasprow Can you remember to do those tests? https://github.com/m-labs/artiq/issues/1080#issuecomment-403336469... https://github.com/m-labs/artiq/issues/1080#issuecomment-406240274
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1080: Also @gkasprow were boards assembled with different silicon revisions of the Ultrascale FPGA? https://github.com/m-labs/artiq/issues/1080#issuecomment-406241202
<GitHub-m-labs> [artiq] gkasprow commented on issue #1080: All FPGAs were purchased at the same time, from same batch so should have same revision. https://github.com/m-labs/artiq/issues/1080#issuecomment-406244909
<GitHub-m-labs> [artiq] gkasprow commented on issue #1080: @sbourdeauducq I remember, but @marmeladapk is on holidays till the end of month.... https://github.com/m-labs/artiq/issues/1080#issuecomment-406246342
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1080: Simplest is probably that you flash ARTIQ into the board. Do you need binaries? https://github.com/m-labs/artiq/issues/1080#issuecomment-406247374
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1080: Simplest is probably that you flash ARTIQ into the board. Do you need binaries?... https://github.com/m-labs/artiq/issues/1080#issuecomment-406247374
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<GitHub-m-labs> [artiq] enjoy-digital commented on issue #1080: @sbourdeauducq: i'll try to do that next week. https://github.com/m-labs/artiq/issues/1080#issuecomment-406254325
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<GitHub-m-labs> [artiq] gkasprow commented on issue #1080: @sbourdeauducq Stupid question: how to program the FLASH (under Windows), but not only part for FPGA but also firmware? ... https://github.com/m-labs/artiq/issues/1080#issuecomment-406286605
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1080: Install the artiq conda package, set up Zadig (http://m-labs.hk/artiq/manual-master/installing.html?highlight=zadig#configuring-openocd), then run ``artiq_flash -t sayma --srcbuild artiq_sayma`` (with ``artiq_sayma`` the name of the folder in the archive I linked).... https://github.com/m-labs/artiq/issues/1080#issuecomment-406287640
<GitHub-m-labs> [artiq] vmsch opened issue #1110: Irregular delays when handling Novogorny sample output https://github.com/m-labs/artiq/issues/1110
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<GitHub-m-labs> [artiq] gkasprow commented on issue #1080: well, i have some problems: ... https://github.com/m-labs/artiq/issues/1080#issuecomment-406332093
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1080: The ``artiq`` package. Not ``artiq-sayma_amc-standalone``. https://github.com/m-labs/artiq/issues/1080#issuecomment-406337832
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<d_n|a> Apologies for another vague "have you seen anything weird" question, but: Any known issues with setting RTIO input gates using from a DMA sequence?
<d_n|a> I still need to create a test case for this issue, but I'm getting an overflow on a .count() following a gate set from the DMA sequence, where there should be at most one event. Same sequence works fine without DMA.
<d_n|a> (I can't think of a reason why set_sensitivity should be different from any other output event in that respect...)
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<rjo> d_n|a: shouldn't. but keep in mind that the overflow can be pretty persistent if the gate is never closed (due to rtio collisions e.g.). make sure it is actually closed before clearing all events, the overflow flag, and starting your dma sequence.
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<GitHub-m-labs> [artiq] gkasprow commented on issue #1080: OK, success. At least from tools point of view. https://github.com/m-labs/artiq/issues/1080#issuecomment-406389149
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<GitHub-m-labs> [artiq] TheCakeIsAPi opened issue #1111: Documentation error https://github.com/m-labs/artiq/issues/1111
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<d_n|a> rjo: Thanks. Could you have a quick look at this test case? https://gist.github.com/klickverbot/b274840ce8e2372d406767a41e20140f
<d_n|a> It works without use_dma, and produces the given output with it set to True. No overflows this time, but still broken. pulsar1_trig -> pulsar1_red_picked_pd is a TTLInOut -> TTLInOut loopback connection with a few hundred nanoseconds of latency (albeit a rather expensive one - I'm not in the lab right now to plug in an actual BNC cable). Am I missing anything obvious?
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<GitHub-m-labs> [artiq] klickverbot opened pull request #1112: test_rtio: Add loopback test using DMA (master...dma-loopback-test) https://github.com/m-labs/artiq/pull/1112
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<d_n|a_> bb-m-labs: force build --branch=pull/1112/merge artiq
<bb-m-labs> build forced [ETA 45m11s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #1730 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1730
<bb-m-labs> build #2523 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2523
<GitHub-m-labs> [artiq] klickverbot opened issue #1113: Setting TTL input gates from DMA doesn't seem to work https://github.com/m-labs/artiq/issues/1113
<d_n|a_> rjo: Nevermind, I've directly moved this to the above issue.
<d_n|a_> Also, is there a way of avoiding the gateware build step on buildbot for software-only changes?