sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1055: ![screenshot_2018-07-09 hmc7043 rev b - hmc7043 pdf](https://user-images.githubusercontent.com/720864/42426028-e8887974-8356-11e8-814e-3b4cfd09865c.png)... https://github.com/m-labs/artiq/issues/1055#issuecomment-403332451
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1055: ![screenshot_2018-07-09 hmc7043 rev b - hmc7043 pdf](https://user-images.githubusercontent.com/720864/42426028-e8887974-8356-11e8-814e-3b4cfd09865c.png)... https://github.com/m-labs/artiq/issues/1055#issuecomment-403332451
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1055: ![screenshot_2018-07-09 hmc7043 rev b - hmc7043 pdf](https://user-images.githubusercontent.com/720864/42426028-e8887974-8356-11e8-814e-3b4cfd09865c.png)... https://github.com/m-labs/artiq/issues/1055#issuecomment-403332451
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1055: So we can work the other way: use documented termination resistor settings (e.g. 100 ohm), then one resistor to 3.3V one one pin, and one to GND on the other, with values that produce the correct voltages at the two ends of the termination resistor. Bonus, we can simply use a DMM to check that the termination settings of this horrible HMC7043 are correct. Consider
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1080: @gkasprow ... https://github.com/m-labs/artiq/issues/1080#issuecomment-403336469
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1080: @gkasprow ... https://github.com/m-labs/artiq/issues/1080#issuecomment-403336469
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<GitHub160> [smoltcp] jhwgh1968 opened pull request #253: [WIP] Implement TCP Window Scaling (master...tcp-window-scaling-phase-2) https://github.com/m-labs/smoltcp/pull/253
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #795: The code is there and somewhat works intermittently, but I cannot do anything until https://github.com/sinara-hw/sinara/issues/567 is resolved. https://github.com/m-labs/artiq/issues/795#issuecomment-403346613
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<sb0> there is vivado 2018.2, might be worth seeing if the crazy PRBS issue is still there
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<GitHub-m-labs> [artiq] hartytp commented on issue #1055: > I don't even see why they suggest RFSYNCIN should be AC-coupled, in some cases you may just send one pulse there, not an AC signal...... https://github.com/m-labs/artiq/issues/1055#issuecomment-403406056
<GitHub-m-labs> [artiq] hartytp commented on issue #1055: @sbourdeauducq also, note that [here](https://ez.analog.com/thread/93030-the-problems-of-hmc7043) an ADI guy says that the RFSYNCIN **should** be dc-coupled... https://github.com/m-labs/artiq/issues/1055#issuecomment-403407377
<GitHub-m-labs> [artiq] hartytp commented on issue #1055: > I don't even see why they suggest RFSYNCIN should be AC-coupled, in some cases you may just send one pulse there, not an AC signal...... https://github.com/m-labs/artiq/issues/1055#issuecomment-403406056
<GitHub-m-labs> [artiq] hartytp commented on issue #1055: > The exact reseeding behaviour is complex, poorly documented, and in some cases, contradictory. The current codebase leaves the "RF reseeder" (reg 3, bit 5) enabled as is the default, which means the SYSREF FSM is stuck in reset ergo the sync can't complete (reg 0x91 stays at the RESET state).... https://github.com/m-labs/artiq/issues/1055#issuecomment-403410861
<GitHub-m-labs> [artiq] hartytp commented on issue #1055: @sbourdeauducq also, note that [here](https://ez.analog.com/thread/93030-the-problems-of-hmc7043) an ADI guy says that the RFSYNCIN **should** be dc-coupled...... https://github.com/m-labs/artiq/issues/1055#issuecomment-403407377
<GitHub-m-labs> [artiq] hartytp commented on issue #1055: I looks like we should also explicitly disable the SYSREF timer once we've finished synchronisation. https://ez.analog.com/message/302525-hmc7043-subharmonics https://github.com/m-labs/artiq/issues/1055#issuecomment-403414319
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1055: We're not using the analog delay (which is noisy anyway) on the high-frequency clocks such as the DAC sample clocks. It is only used on the lower-frequency SYSREF channels.... https://github.com/m-labs/artiq/issues/1055#issuecomment-403420293
<sb0> ffs this new 3.3V bug is getting really annoying
<GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/9153c4d8a334...d2c8e62cb71f
<GitHub-m-labs> artiq/master d2c8e62 Sebastien Bourdeauducq: test_rtio: relax ClockGeneratorLoopback performance requirements
<GitHub-m-labs> artiq/master 423929a Sebastien Bourdeauducq: test: relax min transfer rates from 2MB/s to 1.9MB/s
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1007: After this gets fixed, we should add a device unittest for this. The clock generator loopback test is not a good one, and I made it pass in d2c8e62cb71fea888af1d71f3d9e953840b6cdb4 to stop polluting the CI results, which had been going on for way too long @whitequark. https://github.com/m-labs/artiq/issues/1007#issuecomment-403429478
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to release-3: https://github.com/m-labs/artiq/commit/17665c7271fcb16482f5bdf999a9e8e149042c20
<GitHub-m-labs> artiq/release-3 17665c7 Sebastien Bourdeauducq: test_rtio: relax ClockGeneratorLoopback performance requirements
<GitHub-m-labs> [artiq] jordens commented on issue #1099: also c.f. #686 for tracking various aspects of coredevice performance https://github.com/m-labs/artiq/issues/1099#issuecomment-403430286
<GitHub-m-labs> [artiq] jordens commented on issue #1007: also c.f. #686 for tracking various aspects of coredevice performance https://github.com/m-labs/artiq/issues/1007#issuecomment-403430355
<GitHub-m-labs> [artiq] klickverbot commented on issue #1099: Not to make the issue tracker degrade into a collection of "+1" posts, but let me just stress again I'm still concerned about network transfer rates for medium-term applications – if there is anything in particular I can do to help with making sure things don't regress to even slower speeds than we are currently at, just let me know. (Being able to stream a few MB
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1099: > if there is anything in particular I can do to help with making sure things don't regress to even slower speeds than we are currently at... https://github.com/m-labs/artiq/issues/1099#issuecomment-403437011
<GitHub-m-labs> [artiq] sbourdeauducq closed pull request #1087: compiler: Indirection status of TTuple depends on elements (master...tuple-allocated) https://github.com/m-labs/artiq/pull/1087
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1087: Thanks. https://github.com/m-labs/artiq/pull/1087#issuecomment-403438929
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1087: > (Fixed.)... https://github.com/m-labs/artiq/pull/1087#issuecomment-403438976
<GitHub-m-labs> [artiq] klickverbot commented on issue #1099: Oh, sure, I can spend some time debugging this one issue, and might if it gets critical for us at some point (or investigate alternative hardware platforms). What I meant was more in terms of the bigger picture – I'm quite happy leaving this to whitequark else as there are many other things to spend time on in our experiment, but if there is anything in particular
<bb-m-labs> build #1696 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1696
<GitHub-m-labs> [artiq] klickverbot commented on issue #1087: > Did you mean you have a test case?... https://github.com/m-labs/artiq/pull/1087#issuecomment-403443075
<bb-m-labs> build #890 of artiq-win64-test is complete: Failure [failed conda_create] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/890 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #2495 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2495 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1087: There is PR testing. Just type:... https://github.com/m-labs/artiq/pull/1087#issuecomment-403445186
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<GitHub-m-labs> [misoc] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/misoc/compare/117039bae340...83c835476937
<GitHub-m-labs> misoc/master 83c8354 Sebastien Bourdeauducq: kasli: lower system clock further
<GitHub-m-labs> misoc/master b0a47dd Sebastien Bourdeauducq: kasli: force BUFG insertion on sys_rst...
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1057: All three now seem to pass timing with Vivado 2018.2 and b0a47ddc + 83c83547 on MiSoC. https://github.com/m-labs/artiq/issues/1057#issuecomment-403454435
<bb-m-labs> build #1697 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1697
<bb-m-labs> build #2496 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2496 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<bb-m-labs> build #2497 of artiq is complete: Failure [failed lit_test] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2497 blamelist: David Nadlinger <code@klickverbot.at>
<bb-m-labs> build #444 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/444
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<GitHub-m-labs> [artiq] dhslichter opened issue #1100: FPGA refuses connection https://github.com/m-labs/artiq/issues/1100
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1100: Anything in the board log/UART? https://github.com/m-labs/artiq/issues/1100#issuecomment-403545085
<GitHub-m-labs> [artiq] jbqubit commented on issue #1055: It might be worth opening an Analog Devices service request on this. They may be willing to do a design review of HMC7043 as used on Sayma. https://github.com/m-labs/artiq/issues/1055#issuecomment-403545851
<GitHub-m-labs> [artiq] jbqubit commented on issue #1080: @hartytp Is your board still showing PRBS errors? https://github.com/m-labs/artiq/issues/1080#issuecomment-403547709
<GitHub-m-labs> [artiq] jordens commented on issue #1100: Sounds like https://github.com/m-labs/artiq/issues/986 . doesn't look like it was cherry-picked for release-3 https://github.com/m-labs/artiq/issues/1100#issuecomment-403550034
<GitHub-m-labs> [artiq] jbqubit commented on issue #644: I'll give it a try. Thanks! https://github.com/m-labs/artiq/issues/644#issuecomment-403552089
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1100: It was cherry-picked (9589decd54), but the fix also contained a LLVM update and caused https://github.com/m-labs/artiq/issues/1007. There has been no release since. https://github.com/m-labs/artiq/issues/1100#issuecomment-403553203
<GitHub-m-labs> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/2d4af509c2c284e136b118adf34f3abef6536570
<GitHub-m-labs> artiq/master 2d4af50 Robert Jördens: readthedocs.yml: drop (out of date, not working)
<GitHub-m-labs> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/37e303dafc8af4e1aaae5a26cd3d1643827ff9b1
<GitHub-m-labs> artiq/master 37e303d Robert Jördens: gitmodules: remove empty file
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<bb-m-labs> build #2498 of artiq is complete: Failure [failed lit_test] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2498 blamelist: Robert J?rdens <rj@m-labs.hk>
<bb-m-labs> build #2499 of artiq is complete: Failure [failed lit_test] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2499 blamelist: Robert J?rdens <rj@m-labs.hk>
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/4f56710e4beb1c767dc10f7ddbdc283742540508
<GitHub-m-labs> artiq/master 4f56710 Sebastien Bourdeauducq: grabber: add parser, report detected frame size in core device log
<bb-m-labs> build #2500 of artiq is complete: Failure [failed lit_test] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2500 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<GitHub-m-labs> [artiq] hartytp commented on issue #1080: @jbqubit I don't think there have been any relevant commits since I last tested, so presumably yes.... https://github.com/m-labs/artiq/issues/1080#issuecomment-403584715
<GitHub-m-labs> [artiq] dhslichter commented on issue #1100: @sbourdeauducq haven't looked at the board log or UART, will do so when the event repeats. Does this need to wait for a release until #1007 is addressed or can it come out earlier? https://github.com/m-labs/artiq/issues/1100#issuecomment-403623006
<GitHub-m-labs> [artiq] dhslichter commented on issue #1100: Another traceback, for reference. This has not caused a total crash requiring an FPGA reboot, just killed the currently running kernel, exiting with the error message below:... https://github.com/m-labs/artiq/issues/1100#issuecomment-403653109
<GitHub-m-labs> [artiq] dhslichter commented on issue #1100: Another traceback, for reference. This has not caused a total crash requiring an FPGA reboot, just killed the currently running kernel, exiting with the error message below:... https://github.com/m-labs/artiq/issues/1100#issuecomment-403653109
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1100: > Does this need to wait for a release until #1007 is addressed or can it come out earlier?... https://github.com/m-labs/artiq/issues/1100#issuecomment-403655518