<hartytp>
does this mean that the dqs is terminated at the FPGA and also driven by a controlled impedance?
<hartytp>
i.e. parallel and series termination
<hartytp>
if so, doesn't that give too low an impedance, so it's not optimal for SI?
<hartytp>
also, won't series + parallel termination reduce the signal level?
<hartytp>
finally, since in the design we only use the dqs as an output, why use ODT at all? Isn't controlled impedance drive enough? Or, have I misunderstood how this all works?
<sb0>
_florent_, ^
<hartytp>
this all seems to work fine, so I don't think there is a real issue here, but I was reading the code while doing something else and realised that I don't understand it. So I got curious
<sb0>
DQS should have the same settings as DQ in the platform file. it's only a peculiarity of the PHY that it's not using DQS for reads
<hartytp>
sb0: fine, but it's not clear to me what happens when one combines ODT with an output driver
<hartytp>
sb0: do you have a good way of probing the UFL connectors? If not, I've found that a MCL TMC2-43X+ eval board with traces cut to add 100nF capacitors is an excellent tool for looking at sayma
<GitHub-m-labs>
[artiq] hartytp commented on issue #1083: @gkasprow it would be good if you could repeat that measurement and also probe the GTP_CLK{1,2} FPGA inputs on a board that's not working... https://github.com/m-labs/artiq/issues/1083#issuecomment-402074274
<hartytp>
sb0: okay, that's about all I can do with Sayma for now. I'd like to actually start using it in an experiment soon as a DRTIO slave, but can't do that until the PBRS/SYSREF issues are fixed
<GitHub-m-labs>
[artiq] hartytp commented on issue #1083: > Can this be narrowed down further, i.e. just use the IBUFDS_GTE3 as a clock buffer to the fabric, remove transceivers and all JESD204 stuff, and simplify the SYSREF logic into the minimum code that would demonstrate a problem?... https://github.com/m-labs/artiq/issues/1083#issuecomment-402082794
<GitHub-m-labs>
[artiq] hartytp commented on issue #1083: Fine, however you want to approach it. I'll leave it to you. But, this is a high priority issue for me since it currently prevents me from using Sayma at all. https://github.com/m-labs/artiq/issues/1083#issuecomment-402196988
<_florent_>
hartytp/sb0: we are using the same settings than MIG for the DDR3 in the platform file
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<hartytp>
_florent_: thanks. well, I'm sure it's right, I just don't fully understand what it does. Following the Xilinx black box doesn't give me much more insight. but, I have other things to worry about, so I'll forget about this one for now
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<omid>
sb0, rj0: Do I need to have Vivado 2018.1 in order to run scripts with phaser?
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<GitHub-m-labs>
[artiq] philipkent commented on issue #1092: It looks like it just wasn't created at all. I only have a single directory containing the kc705 gateware at artiq-main/lib/python3.5/site-packages/artiq/binaries/kc705-nist_qc2/. Seems like the artiq package and it's dependencies weren't installed.... https://github.com/m-labs/artiq/issues/1092#issuecomment-402218219
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1092: Ok. Is there a problem other than the artiq package not getting installed? Are things working correctly after installing the artiq package manually? https://github.com/m-labs/artiq/issues/1092#issuecomment-402222474
<rjo>
omid: depends on the script. which one?
<omid>
rjo: For AWG type
<omid>
Also do I need Vivado 2018.1 or .2 for the new phaser build?
<rjo>
omid: the "new" phaser build? could you elaborate?
<rjo>
you need vivado to build for kc705. it doesn't need to be 2018.1 something else should worl as well. but we don't test or guarantee that. you'll have to try.
<omid>
rjo: I meant artiq-kc705-phaser
<omid>
rjo: So in other words if I want to generate dual-tone RF I wouldn't need Vivado?
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<rjo>
omid: if you want to build a bitstream then you need vivado. if you don't want to build a bitstream (i.e. you have one) and if you just want to run experiment scripts to "generate tones", as you say, then you don't need vivado.
<omid>
rjo, sb0: Thanks guys. My phaser's working btw.