sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub-m-labs>
[artiq] mfe5003 commented on issue #1094: I am trying to follow the logic for the RF switch TTL and it looks like for the channel 0 switch the signal just gets processed directly in the CPLD 1:1 based on the input signal.... https://github.com/m-labs/artiq/issues/1094#issuecomment-402330267
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<hartytp>
_florent_, sb0: answering my question about parallel/series termination with bidirectional ports
<hartytp>
on 7-series, there were x_T_DCI IOSTANDARDS which disable the input (parallel) termination whenever the output buffer is active (UG471)
<hartytp>
in ultrascale these aren't supported, any more
<hartytp>
but ug571 seems to imply (without making any unambiguous statements to that effect) that the normal DCI standards now work in the same way as the old T_DCI ones
<hartytp>
i.e. for bidirectional IO it's correct to specify both parallel and series termination (as currently done in the constraints file)
<hartytp>
although, I wasn't sure why you're using the RTT_40 termination instead of the RTT_48, which I would have thought would provide a better match. Is this based on a simulation? Not that it matters, because both should provide pretty good terminations...
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1080: @gkasprow Any update on the clock measurements? I know Tom measured them after they went through the FPGA, but I'd like to double-check. https://github.com/m-labs/artiq/issues/1080#issuecomment-402527541
<GitHub127>
[smoltcp] dlrobertson commented on pull request #252 aa2000f: The size of each Multicast Address Record is not static. In order to calculate the length of the `MLDv2` header and the contained Address Records, we would need to iterate over the contained Address Records. https://github.com/m-labs/smoltcp/pull/252#discussion_r200210699