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[artiq] gkasprow commented on issue #1080: @sbourdeauducq I can flash previous version and check. @marmeladapk can you generate version that had the PRBS issue so I could flash 3 boards and test?... https://github.com/m-labs/artiq/issues/1080#issuecomment-408074425
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[artiq] marmeladapk commented on issue #1080: @sbourdeauducq I'm building 7b75026 + when it finishes I'll build 7b75026 with de7d64d reverted. Can I build without SAWG or is it neccecary here? https://github.com/m-labs/artiq/issues/1080#issuecomment-408079374
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[artiq] marmeladapk commented on issue #1080: @sbourdeauducq I'm building 7b75026 + when it finishes I'll build 7b75026 with de7d64d reverted. Can I build without SAWG or is it necessary here? https://github.com/m-labs/artiq/issues/1080#issuecomment-408079374
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[artiq] gkasprow commented on issue #1080: I've just re-checked with Michal and the same signal that has 1Vpp on transmitter side, has 2Vpp on receiver side and the signal that has 2Vpp on transmitter side has 1Vpp on receiver side. Makes no sense... https://github.com/m-labs/artiq/issues/1080#issuecomment-408086345
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[artiq] gkasprow commented on issue #1080: I checked with multimeter, the trace starts at the HMC chip capacitor and goes to the FPGA. It looks like there was termination missing...... https://github.com/m-labs/artiq/issues/1080#issuecomment-408087193
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[artiq] gkasprow commented on issue #1080: I checked with Ohmmeter before the HMC starts and resistance is higher than a few kOhms so it means that termination did not start calibration yet. After the HMC starts, I measure 40Ohm/70Ohm on CLK2 and 98/96Ohm on CLK1. Since the multimeter uses integrating converter, it does not care about 1Vpp RF signal on it. Difference between measurements with changed leads is
<GitHub-m-labs>
[artiq] gkasprow commented on issue #1080: When I reset the HMC, the FPGA seems to loose the impedance calibration, CLK2 has now 55/72, CLK1 has 250/280. But the resistance I mesure acrross the FPGA input on CLK input does not change when I keep tht HMC in reset state. https://github.com/m-labs/artiq/issues/1080#issuecomment-408097352
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[artiq] gkasprow commented on issue #1080: When I reset the HMC, the FPGA seems to loose the impedance calibration, CLK2 has now 55/72, CLK1 has 250/280. But the resistance I mesure acrross the FPGA input on CLK input does not change when I keep the HMC in reset state. https://github.com/m-labs/artiq/issues/1080#issuecomment-408097352
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[artiq] marmeladapk commented on issue #1080: @sbourdeauducq I want to revert de7d64d. Which pair of those two parameters should I choose? Both are different than what's in de7d64d.... https://github.com/m-labs/artiq/issues/1080#issuecomment-408109381