07:36 <GitHub-m-labs> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/2a7e33e9a46a4dd764faa1694b93e3223e716577

07:36 <GitHub-m-labs> migen/master 2a7e33e David Craven: Emit `default_nettype none.

07:42 <bb-m-labs> build #311 of migen is complete: Failure [failed make_doc] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/311 blamelist: David Craven <david@craven.ch>

11:11 <GitHub-m-labs> [artiq] jordens commented on issue #1149: Around 70 °C https://github.com/m-labs/artiq/issues/1149#issuecomment-419876865

12:18 <acathla> Hi. What's the difference between de0cv, de0nano and de0nanosoc ? And is there any documentation on how to port migen/misoc to another platform?

12:33 <cr1901_modern> acathla: https://www.wdj-consulting.com/blog/migen-port.html

12:33 <cr1901_modern> Disclaimer: This is my website

12:34 <cr1901_modern> Idk the difference between the de0s; the only Altera board I have is a Cyclone 2 from 2007

12:35 <GitHub-m-labs> [artiq] sbourdeauducq pushed 4 new commits to switching: https://github.com/m-labs/artiq/compare/014cfd8dbd82...663432adbdbd

12:35 <GitHub-m-labs> artiq/switching bc1d3fd Sebastien Bourdeauducq: satman: ping repeater links...

12:35 <GitHub-m-labs> artiq/switching 31bef99 Sebastien Bourdeauducq: firmware: fix drtio_routing compatibility with master and satellite

12:35 <GitHub-m-labs> artiq/switching 7ec45ef Sebastien Bourdeauducq: kasli: add missing cri_con to Satellite

12:35 <acathla> I have a DE2 with a Cyclone II too, but it's just to learn how to port a new board and use migen or misoc with it

12:35 <acathla> thank you for you website

12:36 <cr1901_modern> That would also be my board (or some variant of it). I don't even remember the version of Quartus that can compile it, but I would be wary if such an old version of Quartus works with Migen

12:37 <cr1901_modern> Unless they keep the command-line interface portion to Quartus very stable between versions.

12:37 <cr1901_modern> acathla: Np. Good luck :). I'm afraid I can't help w/ your specific board

12:43 <acathla> I installed Quartus II 32 bits version 13.0.1 for that board.

12:51 <key2> does a

12:51 <key2> Record() necessarely end up in regs ?

12:51 <key2> meaning the signals

12:51 <cr1901_modern> no

13:41 <GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to switching: https://github.com/m-labs/artiq/commit/4d889c0c4ebd3354d8fc966621b815d976200006

13:41 <GitHub-m-labs> artiq/switching 4d889c0 Sebastien Bourdeauducq: firmware: improve DRTIO log messages

14:43 <sb0> what are the use cases for building the runtime with !has_rtio_core or !has_ethmac again?

14:48 <rjo1> no idea. wouldn't drtio be !has_ethmac?

14:49 <GitHub-m-labs> [artiq] sbourdeauducq pushed 3 new commits to switching: https://github.com/m-labs/artiq/compare/4d889c0c4ebd...19a14b68b15c

14:49 <GitHub-m-labs> artiq/switching 19a14b6 Sebastien Bourdeauducq: runtime: program DRTIO routing table into gateware

14:49 <GitHub-m-labs> artiq/switching 264078b Sebastien Bourdeauducq: style

14:49 <GitHub-m-labs> artiq/switching e01efbc Sebastien Bourdeauducq: runtime: merge sync_tsc and wait_tsc_ack

14:49 <sb0> drtio (satellites) use a different firmware

14:50 <sb0> has_ethmac is useful there in bootloader and libboard_misoc, but I don't see why should the runtime be buildable without ethernet

15:43 <key2> someone has an openocd configuration for multiple xilinx jtag daisy chained ?

16:35 <rjo> key2: sayma. see artiq_flash in artiq.

16:42 <acathla> cr1901_modern, it works! Well, it builds, first try, but all the 5 LED just blink. In your example : m.comb += [plat.request("user_led").eq(m.d1) for l in [m.d1, m.d2, m.d3, m.d4, m.d5]] , I don't get the meaning of the for loop here

16:47 <acathla> Ok it's corrected in the file as gist

17:05 <key2> rjo: https://github.com/m-labs/artiq/blob/e7dba344759c0d72f163d59843e44a61eb9dc0fa/artiq/frontend/artiq_flash.py ?

18:42 <rjo> key2: yes

18:43 <key2> thx worked