00:58 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1155: > If it is, then I wonder why we can't get the master into a deterministic state without the manual reset.... https://github.com/m-labs/artiq/issues/1155#issuecomment-422609547

01:00 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1155: > If it is, then I wonder why we can't get the master into a deterministic state without the manual reset.... https://github.com/m-labs/artiq/issues/1155#issuecomment-422609547

01:14 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1155: Hmm, the reset should already be there:... https://github.com/m-labs/artiq/issues/1155#issuecomment-422612379

03:16 <GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to switching: https://github.com/m-labs/artiq/commit/62642957cd9e36c6e87cd2ca4aabfba8c616d71b

03:16 <GitHub-m-labs> artiq/switching 6264295 Sebastien Bourdeauducq: runtime: fix DRTIO aux channel race condition

05:29 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1129: @marmeladapk From your comment https://github.com/sinara-hw/sinara/issues/557#issuecomment-422415161... https://github.com/m-labs/artiq/issues/1129#issuecomment-422658469

05:38 <GitHub-m-labs> [artiq] sbourdeauducq commented on commit b482f5f: @whitequark Can this go on release-3 as well? https://github.com/m-labs/artiq/commit/b482f5feaedde7bd10903fd9e7cad249e596f88b#commitcomment-30556867

07:44 <GitHub-m-labs> [artiq] whitequark commented on commit b482f5f: OK https://github.com/m-labs/artiq/commit/b482f5feaedde7bd10903fd9e7cad249e596f88b#commitcomment-30557980

08:47 <GitHub-m-labs> [artiq] gkasprow commented on issue #1129: one working board was shipped to you, another to Tom.... https://github.com/m-labs/artiq/issues/1129#issuecomment-422713672

08:48 <GitHub-m-labs> [artiq] hartytp commented on issue #1129: @gkasprow well, since we are most likely going to scrap the HMC7043 in the next revision, is it worth tracking this down further? I'm implementing the new synchronization scheme right now... https://github.com/m-labs/artiq/issues/1129#issuecomment-422714077

09:03 <GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to switching: https://github.com/m-labs/artiq/commit/142c952e3d24fba16c48df7c2e58ab78a5baf3c6

09:03 <GitHub-m-labs> artiq/switching 142c952 Sebastien Bourdeauducq: drtio: implement per-destination underflow margins

09:06 <GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to switching: https://github.com/m-labs/artiq/commit/3d965910f7e326467c84bc35d5ab68b7b5250025

09:06 <GitHub-m-labs> artiq/switching 3d96591 Sebastien Bourdeauducq: Revert "drtio: implement per-destination underflow margins"...

09:22 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1129: I had asked @jbqubit by email, but no reply so far. https://github.com/m-labs/artiq/issues/1129#issuecomment-422724516

12:57 <GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to switching: https://github.com/m-labs/artiq/compare/3d965910f7e3...b86b6dcc0965

12:57 <GitHub-m-labs> artiq/switching b86b6dc Sebastien Bourdeauducq: drtio: add switching input test

12:57 <GitHub-m-labs> artiq/switching 08be176 Sebastien Bourdeauducq: drtio: fix satellite i_status handling

12:57 <GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/69d060b639f6f0968b59f02cbc104e752f78d0a8

12:57 <GitHub-m-labs> artiq/master 69d060b Sebastien Bourdeauducq: drtio: fix satellite i_status handling

13:23 <sb0> http://www.cost.eu/COST_Actions/ca/CA17113

14:10 <GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to release-3: https://github.com/m-labs/artiq/commit/fb1dfcf3729d9bd4ebcfc16da0590a0ebde2ca39

14:10 <GitHub-m-labs> artiq/release-3 fb1dfcf Sebastien Bourdeauducq: firmware: Use larger ARP cache...

14:43 <GitHub-m-labs> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/4621abca89bed9b22b27c4934268a62f7f7ff52e

14:43 <GitHub-m-labs> migen/master 4621abc hartytp: sayma rtm: add clock mezzanine GPIO (#133)

15:03 <bb-m-labs> build #313 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/313

15:14 <bb-m-labs> build #947 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/947 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

15:14 <bb-m-labs> build #2607 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2607 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

15:16 <hartytp> sb0: building sayma rtm with latest migen, I'm getting errors like "ERROR: [Synth 8-3966] non-net port hmc_spi_clk cannot be of mode inout: `default_nettype is "none" [/home/tph/scratch/artiq_sayma/rtm_gateware/rtm.v:50] "

15:16 <hartytp> is this related to 2a7e33e9a46a4dd764faa1694b93e3223e716577

15:16 <sb0> ah, I would have been surprised if at least one shitty EDA tool didn't choke on default nettype none

15:17 <GitHub-m-labs> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/1d3433edf7925221faf2c47c148aa4204a518fd4

15:17 <GitHub-m-labs> migen/master 1d3433e Sebastien Bourdeauducq: Revert "Emit `default_nettype none."...

15:18 <cr1901_modern> How many years of your life do you think you've lost trying to search for the subset of Verilog that makes all synthesizers happy?

15:18 <hartytp> ta

15:19 <hartytp> yes, that did it

15:22 <sb0> right now it seems this vivado trash is miscompiling the drtio packet serialization logic for the read_reply packet, after I made unrelated changes to implement switching

15:22 <bb-m-labs> build #314 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/314

15:23 <sb0> for some reason, having large registers and doing bit shifts on them seems to tickle bugs

15:24 <sb0> this bullshit wasted like a month when implementing DMA

15:27 <hartytp> nasty

16:21 <sb0> hartytp: things other than inputs are working on the other hand

16:23 <sb0> narrowing the problem down; it's the satellite sending the wrong packet content; the packet length is correct but all bits after and including position 32 are zeroed out

16:23 <sb0> if I hardcode some other value there, then it goes through

16:24 <sb0> I guess I can rewrite the value generation code in a way that makes the vivado garbage happier

19:10 <GitHub-m-labs> [artiq] whitequark commented on issue #733: LLD is production-ready since LLVM 7.0. https://lists.llvm.org/pipermail/llvm-announce/2018-September/000080.html https://github.com/m-labs/artiq/issues/733#issuecomment-422923629