<Astro-_>
hartytp is more knowledgable about the values that work
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<mtrbot-ml>
[mattermost] <pathfinder49> @astro The TEC-SHDN pins PP2/3 are not configured. These need to be high to enable the TEC.
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<bradbqc>
Does anyone have any experience with using an external 1GHz clock to drive the urukul and 9910s? rjo I believe I see your name on the relevant commits. In the device db I've set refclk to 1e9 and clk_div to 1 for cpld, and I've set pll_en to 0 for the 9910 channels but the frequency output we're getting seems to be divided by 4 (i.e. if I set it to
<bradbqc>
100 MHz, the output is 25), and it can't output anything over 125 MHz. Am I missing something in the device db
<bradbqc>
?
<bradbqc>
Also set clk_sel to 1 for the front panel sma
<rjo>
could be old urukul cpld gateware
<bradbqc>
How old would it have to be to cause problems? The gateware is using my personal fork of ARTIQ, which is at most 2-3 months behind m-labs'
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<rjo>
roughly the time of the commits you are referring to. quartiq flashes the current gateware. with other vendors i don't know. urukul cpld gateware is independent of the kasli gateware.
<rjo>
so it depends on where you got your urukul from and what's been done with it.
<bradbqc>
Ah, I see. We ordered this kasli box (including the urukul) over the summer and the only gateware I've changed is kasli's, so it should be recent enough, right?
<bradbqc>
And I'm not actually sure what company put the hardware together. The quote we got was directly from m-labs
<_whitenotifier-f>
[nmigen] codecov[bot] commented on pull request #266: Record: force name to be given by name for `__init__()` - https://git.io/JeVW1