<wolfspraul> theregister.co.uk has a picture of M1 on their homepage :-)
<kristianpaul> oh, wow
<lekernel> ah, the icalepcs people ask me about my institution. should I answer "radical tech coalition"? :-)
<lekernel> argh, Masala has problems cutting the > 10GB video files... the saga continues
<lekernel> should I explain them how to use dd?
<kristianpaul> or 7z :)
<lekernel> anything that works on mac too?
<wpwrak> dd ? :)
<wpwrak> or tar --multi-volume --tape-length KILOBYTES
<wpwrak> of course, all this is probably too old-school for iLovers ... :)
<cde> hello milkymist
<kristianpaul> hi
<wolfspraul> hi
<zer0her0> oh hai
<zer0her0> lekernel, knowing the bare min about FPGA, it looks good and engaging even for a newb like myself.
<wpwrak> lekernel: nice first slide. i can see where it's coming from ;-)
<wpwrak> we should take a poll of how many people would consider "a FPGA" a typo :)
<cde> lekernel: looking forward to having a GPLv3 replacement to ISE :)
<wpwrak> lekernel: looks great ! i hope they hire you right away to work on that ;-)
<wpwrak> btw, what is 1/2/3-hot ?
<stekern> yeah, those slides are really good
<larsc> looks forward having a bsd or gpl2 replacement to ISE ...
<larsc> wpwrak: I only know 1-hot, which is only one bit is set at a time in a word
<larsc> but i suppose 2/3-hot means 2 bit/3bits set at a time
<larsc> suppose you have a counter where you want let a different action take place for each value
<larsc> instead of using a binary counter and a lot of comparators, you'd use a one-hot counter with a shifter
<wpwrak> makes sense. thanks !
<DJTachyon> man i need a new computer
<kristianpaul> 10usd but you dont count rework isnt?
<kristianpaul> Or there is a cheap alterntive like a swapble bga socket?
<stekern> kristianpaul: pcb's aren't very expensive, just throw the board if you fail. besides, AFAIK there are still non-bga FPGAs out there
<kristianpaul> that could be a solution yes
<kristianpaul> (non-bga) there are, but al the LUTs you want but even for spartan-6 there are some QFN i remenber
<kristianpaul> checking backlog sebastien pointed for SOT-23 already
<stekern> yeah, but the size isn't so important for the purposes said in the slides
<kristianpaul> indeed
<mumptai> but only for the small models
<wpwrak> if you expect to go through a lot of boards, you could even make a board with just the FPGA and some cheap header. put the rest of the circuit on a separate board
<lekernel> 2-hot means two 1-hot codes concatenated together (see the diagram below)
<wpwrak> yeah, i'm trying to make sense of that :) looks like a 12:1 demultiplexer
<wpwrak> and 1-hot would be a word in which exactly one bit is "1" ?
<lekernel> yes, it is
<lekernel> yes
<lekernel> it's a multiplexer btw... well, in fact it can be used both ways, but it seems xilinx adds a buffer at the output to drive the wire, and it becomes unidirectional
<wpwrak> (demux) yeah, right
<cde> I don't get it. Xilinx does make little money on the software part. They would loose little by open-sourcing their tools
<wpwrak> a pair of demuxes controlling a mux :)
<wpwrak> cde: it may be something that goes against their belief system ...
<cde> yes, I guess so
<lekernel> I have talked to one of their managers about that, and the answer is "they won't"
<lekernel> if someone asks, I could explain that in detail during the talk, but it's not very interesting compared to the other content
<wpwrak> cde: besides, "open-sourcing" is often complicated by code containing items licensed from others. you get this often in commercial code. once it's old enough, nobody quite remembers the legal state of it all. so it can be quite hard to open it.
<lekernel> so only if time allows/people are interested in hearing that
<cde> it's a pity. we are wasting good time and effort in re-doing what's already being done
<lekernel> and yes, cross-licensing is one of the reasons
<cde> hmm
<lekernel> kristianpaul: there are BGA sockets
<stekern> and then there are those companies that refuse to touch/use anything that is open source (the "who can we sue?" argument)
<lekernel> and yes you can also make throwaway breakouts
<lekernel> ok, well
<larsc> lekernel: did you ask him whether he considered the hardware or the software their product?
<lekernel> 1) They do not want to support customers using broken bitstreams. It is too easy to produce subtly buggy designs or perhaps even damage chips if you fiddle with the P&R and bitstream generator. They want to keep that part under their control.
<lekernel> 2) Their large customers and IP providers believe in "security by obscurity", and they see the undocumented bitstream format as an additional layer of protection for their designs.
<lekernel> 3) They want to make it harder for their competitor to copy them.
<wpwrak> 4) they may also fear exposing things a patent troll could sink his fangs in
<lekernel> maybe, but those are the reasons they exposed
<lekernel> and the "cross licensing" arguments comes from the fact that the lattice tools are exactly the same :)
<stekern> 4 they would probably not admit ;)
<wpwrak> the "oh the support" argument is quite common. i wonder if it actually ever works that way. there are cases where fraudulent commercial products are incorrectly attributed to the original company and cause support cost and/or tarnish their reputation, but that's a bit different.
<larsc> i would suspect that their tools codebase is really a unmaintanable mess anyway. and will colllapse onto them someday
<wpwrak> larsc: maybe it's "too big to fail" ;-)
<lekernel> larsc, certainly. this also makes it less interesting for everyone that they open it.
<wpwrak> you can probably do better with a fresh mind and modern knowledge than trying to teleport a dinosaur into the modern age
<larsc> exactly what i was thinking
<larsc> if there is a good opensource alternative they will probably consider supporting it at some point
<lekernel> until mid-2008 they needed a driver that exposed PCI/DMA access into userspace to _try_ to get their USB (yes!) JTAG cables to work
<lekernel> god! that was fucked up
<wpwrak> i must admit, however, that i'm quite impressed by those projects that have succeeded to do just that. e.g., mozilla and open/libreoffice.
<lekernel> it almost never worked and kernel-paniced the machine on 60% of JTAG transfers
<cde> lekernel, the same arguments could be made for proprietary UNIX systems in the 90's
<cde> then came Linux
<wpwrak> larsc: we don't see many CPU vendors diss gcc these days, do we ? ;-)
<wpwrak> lekernel: at least they didn't require a PCI-to-ISA converter ... ;-)
<lekernel> now they still have FPGA Editor based on the magnificient Wind/U toolkit (iirc by the same company who committed that "USB driver")
<larsc> wpwrak: i was just thinking that it eventually becomes a competitive advantage
<wpwrak> larsc: yeah, eventually, one of the companies will defect and embrace open source. usually, in the first generation it's one that's about to go down and they hope for some magic savior to come from open source. i don't think that has ever worked :)
<wpwrak> larsc: but in the next round, things will get more sane. etc. time works in our favour ;-)
<lekernel> that thing uses sunrpc apparently for intra-process communication between threads and doesn't grok DISPLAY=:0.0 (you need to set it to :0 before running)
<lekernel> it's also extremely ugly, buggy and prone to crashes
<lekernel> there are basic flaws like the file open dialog will fail if you have more than a few dozen characters in your path
<wpwrak> if uses X ? how modern. i hope it's to emulate a tek4014, for which all the rest of the software is optimized :)
<lekernel> yes with Motif lol
<wpwrak> leaving no grave unopened, eh ? :)
<lekernel> I wonder how good Python would be for FPGA toolchain
<lekernel> there is nice stuff, like NetworkX, built-in sets, lists, dictionaries, etc.
<lekernel> would make my life much easier compared to C
<lekernel> if the end result isn't unusably slow, that would be a great choice
<larsc> it will probably be good for prototyping
<larsc> but p&r and python will be dead slow I guess
<wpwrak> it's probably all love and sweetness until the day comes when you need to optimize the thing
<wpwrak> and that day invariably comes for this sort of operations :)
<larsc> myhdl on the other hand is great, because python allows you to create sort of your own DSL while still being able to use all the existing libraries
<wpwrak> i'd actually consider C pretty nice for "algorithmic kernels".
<wpwrak> larsc: but what happens when you try to synthesize something that uses these libraries >
<larsc> the libraries are only used for simulation
<wpwrak> i'm a bit suspicious about myhdl. if something looks too good to be true, it usually isnt :)
<larsc> it is a fresh alternative to verilog and vhdl
<kristianpaul> btw you get verilog from that myhdl anyway..
<larsc> and it is backwards compatible
<wpwrak> yes, i've seen it. the language as such looks quite decent. but i wonder what happens underneath.
<larsc> magic :)
<kristianpaul> lekernel: is worthless to mention some efforts in the past from iverilog about trying to support as addon EDIF out too?
<kristianpaul> about bga socket, nice!, you even can consider a fpga upgrade at seems s6 keeps pin compatibillity :)
<wpwrak> (bga socket) be warned that they're usually quite expensive
<lekernel> myhdl is nice. the verilog/vhdl conversion is quite hacky though.
<wpwrak> i suspected as much :)
<lekernel> also patches I send three weeks ago are still not merged, grmbl
<larsc> but it is important to have it since it offers you a way to synthesize your code without having native support in myhdl for it
<larsc> makes it sort of usable
<lekernel> kristianpaul: iverilog synthesis never did much and it's dropped now
<larsc> it's like the early c++ compilers which would generate c code
<larsc> "compilers"
<lekernel> well... I rather think of myhdl as a way to generate lower-level verilog by the metric ton from python and higher level constructs
<lekernel> it can still make sense to have this layer, just like c/c++ compilers still generate "human-readable" assembler
<larsc> but aren't netlist sort of the assembler counterpart?
<larsc> on the other hand you can write netlists in verilog
<larsc> hm looks as if i'm moving with less then some people go on holiday with. one bag of cloths, one bag of electronics
<wpwrak> so you're not fully virtualized yet ? :)
<larsc> nope
<larsc> not an AI, yet ;)
<larsc> but moving is always a great opportunity to get rid of ballast
<wpwrak> yeah. at least in theory :)
<wpwrak> it helps if you move across continents, though. there you really have a strong motivation to get rid of some of the old junk.
<larsc> i only booked a flight ticket with 20kg of luggage included
<wpwrak> where are you moving ?
<larsc> munich
<larsc> so I could have taken more
<wpwrak> yeah, you can always order a container :)
<larsc> most of my equipment has already become inventory of the local hacker space so i'm leaving it there
<wpwrak> ;-))
<larsc> i moved most of my other stuff to my parents house, so i'll properly take more with me when i'm visiting them for christmas
<kristianpaul> lekernel: do you have publix visit stats of your site?
<kristianpaul> jsut curious :)