<jonand>
I now have the mm rc3 pcb stackup in cadence sigxplorer. Although the layout is very good on the MII bus (no layer changes, good reference to ground plane) it could use a 22 or 33 ohm series resistor
<jonand>
without it there is some minor ringing
<jonand>
not alarming though, it will for sure work good anyway
<jonand>
but if you guys run into EMI problems this could be a place to start
<wolfspraul>
22 or 33 ohm series resistor where?
<jonand>
on the MII bus between the fpga and the ethernet phy
<jonand>
in the driver ends, that is. 4 at the fpga and 4 at the phy. but as I said, it looks decent anyway.
<wolfspraul>
what's your advice? should we change it proactively, or just keep an eye on it / wishlist?
<jonand>
It really depends on how bad it looks in reality. Did you run the EMI tests with ethernet traffic or are the ethernet + usb ports considered as "service ports" (that do not need testing because they are not connected during normal operation)?
<jonand>
If a re-layout for some reason means that the MII bus need to switch layer it is a good idea to add the series resistors
<jonand>
I'm trying to run a worst-case (strongest, weakest) model but I and the simulator are not friends today....
<jonand>
any recommendation for a pastebin service for pictures so I can show some screen dumps?
<wolfspraul>
good question about 'service ports'
<wolfspraul>
we ran 'typical' use cases
<wolfspraul>
but they are not properly documented, and the boundary to the 'service ports' is not clear
<jonand>
as you can see you get a tiny rise/fall time penalty but at 25MHz it's nothing really
<jonand>
my wet dream are simulations like these in Ki-cad
<jonand>
"how hard can it be?" :)
<jonand>
I really have no clue on how to take ibis (or spice) models, add transmission line (microstrip, stripline and so on) math and feed that output into gnuplot
<jonand>
I just use the commersial tools like black boxes and am happy that what I see in the lab looks very much like what I get from the tools.
<jonand>
But it would be very cool to get features like this in open tools.
<jonand>
hey, why feed it into gnuplot when you could display it on stage with the milkymist? :D
<GitHub98>
[flickernoise] xiangfu pushed 2 new commits to master: http://git.io/0kEjvg
<GitHub98>
[flickernoise/master] use one PrtScr/SysRq for take screenshot - Xiangfu
<GitHub98>
[flickernoise/master] gui/audio: remove the mic boost ioctl - Xiangfu
<wolfspraul>
jonand: excellent stuff, thanks a lot!
<wolfspraul>
feel free to do more simulations, we can't get enough of this stuff :-)
<wolfspraul>
do we want to add the suggested series terminators?
<jonand>
not from a functionality point of view. add them if a relayout makes you change layers (the current bus is on top layer only) or if you run into EMI problems while using ethernet.
<wolfspraul>
makes sense, thanks a lot!
<wolfspraul>
we are currently debating whether to switch from the current 6-layer to a 8-layer layout
<wolfspraul>
that's because the new revision R4 introduces some more wires such as digital video (dvi-i combining vga + digital)
<wolfspraul>
so we are not sure whether or how well it can fit into the existing 6-layer layout
<wolfspraul>
we will know more soon :-)
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<wpwrak>
(image upload) how about setting up an account on downloads.qi-hardware.com ? that's convenient for uploads (with rsync or scp)
<wpwrak>
jonand: one limitation we (currently only, i hope) have is that we don't have expensive lab instruments. e.g., the fastest scopes used regularly in the M1/qi-hw universe are 100 MHz DSOs with passive probes. so this sort of ringing would be completely invisible to us by measurement.
<wpwrak>
this means that we have to rely on (hopefully good) design rules and simulation, with only very coarse feedback (of the pass/fail type)
<wpwrak>
regarding the simulation, this looks like something qucs could handle. we'd have to find a model for the I/Os, though.
<wpwrak>
what this model doesn't show are crosstalk and such. would you normally examine these too ? if yes, how would you model them ?
<wpwrak>
(qucs) qucs may not be the best choice for design-driven simulation, though. it seems that spice is both faster and harder to derail. the drawback is of course that spice isn't meant for human users ...
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<lekernel>
wpwrak: there are IBIS models published by the various chip vendors, but I don't know how they work internally
<jonand>
You typically never get spice models from the chip vendors. The reason I've heard is that they reveal too much about the internals of the chip. I guess this is typically a problem for TSMC/UMC/IBM/Toshiba/TI or whatever chip house fabless people are using these days
<jonand>
IBIS models are on the other hand most of the time pretty easy available.
<jonand>
Most IBIS models state in the header "derived from spice bla bla" and if they work at all the simulation results are pretty correct
<wpwrak>
is there a straightforward conversion to spice ?
<jonand>
That's at least my experience with ~10 models
<wpwrak>
or is there anything in the way IBIS works that would trip spice ?
<jonand>
wpwrak: don't be sorry that you can't afford a top of the line scope, in today's microvia designs with 0.5mm bga pitch there is nowhere to put the probe anyway, and even if you can reach a via it is most certainly not at the receiver end so your measurement isn't that useful anyway..
<jonand>
.. and noone can afford the time to measure signal integrity on 128bit databuses by hand either...
<jonand>
wow, eispice looks interesting, I'll definitely have a look
<wpwrak>
(measure) yeah, a full verification would be crazy :)
<Hodapp>
Is SPICE used much with more complex digital designs? I've primarily seen it for analog.
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<jonand>
I've heard that some "top tier" customers require spice models from e.g. Xilinx so that's why they are available for top models like Virtex
<jonand>
I'd say that IBIS is what everyone <500MHz (cycle time) is using. Haven't done any DDR3 myself so I don't know if it is needed.
<wpwrak>
lekernel: should be easy to pull off with M1 :)
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<wpwrak>
(eispice) unfortunately, it looks a bit abandoned. last release almost 5 years ago. mailing list eerily quiet.
<wpwrak>
of course, the *spice world doesn't seem to be in a great hurry in general. just saw that the spice referenced for ideas in eispice has a manual from 1998. well, i guess nothing really new happened since the transistor ;-)