lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs :: EHSM Berlin Dec 28-30 http://ehsm.eu :: latest video http://www.youtube.com/playlist?list=PL181AAD8063FCC9DC
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<lekernel> hmm... how does one generate and receive 1080p60 video signals? bit clock is 1485MHz, and artix-7 serdes are only 1250MHz (altera is worse)
<lekernel> ("3 lanes at 10x serialization rate up to 1.95 Gbit/s" of course, the 1.95 Gbit/s is all three channels combined)
<lekernel> kintex has 1600MHz serdes but they are super expensive
<Fallenou> maybe nobody does :) maybe they do 1080i60 or 1080p30
<lekernel> according to xrandr my laptop lcd is in 1080p50
<larsc> we use a hdmi phy which does serial->parallel
<lekernel> The Sil9002 discrete HDMI® PHY transmitter PHY is designed to work exclusively with Silicon Image's transmitter IP that is integrated by MPEG system-on-a-chip (SoC) silicon manufacturers.
<larsc> our image transmitter IP is opensource
<larsc> but it's just a dumb framebuffer
<lekernel> ah, thanks!
<Fallenou> larsc: you work at AD ?
<lekernel> "The ADV7511 interface consists of a 16bit YCbCr 422" huh
<lekernel> HDMI is RGB, no?
<Fallenou> maybe it gets translated into rgb
<lekernel> anyway, interesting that only adi seems to be making fast serdes ...
<larsc> Fallenou: yes
<lekernel> yes you can switch between YCbCr and RGB (ie disable the color space transform of the adi chip)
<Fallenou> nice :)
<larsc> lekernel: hdmi is both YCbCr and RGB
<larsc> the adv7511 supports both YCbCr and RGB in and out
<larsc> and has a CSC which allows you to convert if neccessary
<lekernel> larsc: I'd actually love a dumb bidirectional high-speed serdes. just to solve the "slow FPGA I/O" problem.
<lekernel> even a 1:2 serdes would do the trick
<lekernel> (and require fewer pcb traces)
<larsc> the adv7511 is not so dumb, input is only the video stream, but everything of the hdmi protocol is generated on the device
<lekernel> yes, I see that, even HDCP
<lekernel> $119 ?!
<lekernel> others are $1k-$2k
<lekernel> there's another one at $137
<lekernel> also with CES9919
<lekernel> are those 90% dysfunctional chips? :-)
<larsc> hm: "1-$1,497.000" and "6-$149.7000" somebody put the decimal point at the wrong place?
<lekernel> all CES9919 chips are much cheaper
<lekernel> I guess they don't work
<larsc> maybe they just list it and hope somebody buys it by accident ;)
<lekernel> so it seems that options are
<lekernel> 1) artix-7 and 720p or 1080p30 only
<lekernel> 2) artix-7 and fat, messy and slightly expensive chips for 1080p60 (which also remove the possibility of bidirectional hdmi ports)
<lekernel> 3) very expensive kintex-7
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<lekernel> for sampling you might be able to use two serdes and 180° clocks :) but it's kinda risky
<lekernel> and for transmitting... maybe with some external buffering/muxing... if I want to play with 1.5GHz discrete logic on a PCB ;)
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<Alarm> git clone git://github.com/fallen/rtems-milkymist.git is dead ?
<kristianpaul> migrated
<kristianpaul> upstream
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<Alarm> upstream = ?
<larsc> merged in the rtems project
<larsc> rtems.org
<Alarm> ok
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<lekernel> roh: does bootlab still exist?
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<lekernel> hey Lattice has 3200MHz SERDES
<lekernel> unless I read it wrong ...
<Fallenou> hey I have an ECP3 board :)
<lekernel> do they still sell them for cheap?
<Fallenou> it was $99
<Fallenou> the versa kit
<Fallenou> dunno if they still sell them
<lekernel> it's $299 now
<Fallenou> hum yep price gone up again
<Fallenou> would you switch to lattice ? :)
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<lekernel> how's the software? I tried it a few years ago and it was much worse than ISE
<Fallenou> well it's an ISE clone
<Fallenou> I see almost no difference except the name
<Fallenou> I had to use windows IIRC to flash the board
<Fallenou> in a virtualbox it worked fine
<lekernel> azonenberg: you there?
<azonenberg> lekernel: yep
<azonenberg> This is probably a better forum for this discussion than FB :P
<lekernel> as far I know the S6 transceivers work indeed to 3+GHz, but only with signals that have an embedded clock
<azonenberg> anyway so have you considered using spartan6 lxt serdes?
<azonenberg> You're transmitting, right?
<lekernel> serdes != transceiver
<azonenberg> or do you need to receive too
<lekernel> at least in xilinx terminology. now it could be that lattice calls serdes what xilinx calls transceiver
<azonenberg> whats the difference? I know the GTPs can do clock recovery and the s6 serdes cannot
<azonenberg> is that it?
<azonenberg> but "can do" and "must do" arent the same thing
<lekernel> yes, but can this clock recovery be disabled?
<lekernel> and use a supplied clock instead?
<lekernel> AFAIK in S6 the SERDES use an I/O clock generated by PLL+BUFPLL
<lekernel> and the GTP contain their own PLL, recover clock from the incoming signal, and transfer the data to the fabric/user clock with built-in FIFOs and such
<azonenberg> hmm, interesting
<azonenberg> so the gtp is a serdes + clock recovery + other stuff
<azonenberg> i've never used them
<lekernel> I think you cannot clock the GTP from anything else than its built-in PLL that locks on the incoming signal, but I might be wrong
<azonenberg> i looked briefly at IOSERDES
<lekernel> and yes, the GTPs are big and complex beasts
<azonenberg> But again, refresh my memory
<azonenberg> what is the application here, do you need to accept video in?
<azonenberg> i thought this was only for generating video
<lekernel> IOSERDES are merely shift registers + layers of flip flops
<azonenberg> because for *sending* vidoe, the IOSERDES should work fine
<azonenberg> video*
<lekernel> not in 1080p60
<azonenberg> and at higher speed, the GTPs should be usable
<lekernel> won't the GTP enforce some encoding that permits clock recovery on the receiving side and is not what should be used for HDMI?
<azonenberg> Thats what i'm wondering
<azonenberg> does it mandate IBM 8b10b?
<azonenberg> like i said i've never actually used the GTPs
<lekernel> and yes I need to receive video too
<azonenberg> Well in that case if the gtp requires clock recovery that wont work
<azonenberg> phase-shifted sampling may or may not, but i'm inclined to say no
<azonenberg> the limit is not just Fclk, it's setup/hold times too
<azonenberg> which the incoming phase-shifted data will likely not respect
<lekernel> ah and yes, Lattice's SERDES are Xilinx's transceivers
<azonenberg> Can they be used as dumb SERDES?
<azonenberg> if they run at 3.2 Gbps they're almost certainly CML + 8b10b as used in infiniband, SATA, etc
<azonenberg> that seems to be turning into an industry standard for gigabit serial
<azonenberg> HDMI is the lone holdout
* azonenberg wonders when we'll see a GTP-compatible video standard coming out
<lekernel> seems s
<lekernel> o
<lekernel> they have generic SERDES and 8b10b modes
<azonenberg> interesting
<lekernel> maybe xilinx transceivers can work this way too... hmm
<lekernel> but why doesn't the xilinx dvi demo use those? hmm
* azonenberg pulls UG386
<lekernel> LatticeECP3 FPGA devices to transmit and receive the TMDS signaling used by DVI and HDMI and achieving up to a full 1.65Gbps data rate in the low-cost FPGA.
<azonenberg> interesting
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<lekernel> so, this is explicitly supported here
<azonenberg> "The actual width of the port depends on the GTPA1_DUAL tile’s INTDATAWIDTH setting (controls the width of the internal datapath), and whether or not the 8B/10B encoder is enabled."
<azonenberg> So the s6 GTP should be capable of transmitting TMDS with the GTPs
<lekernel> only 720p/1080i
<azonenberg> not sure about receiving
<azonenberg> and that appnote is supposed to be about using the lowest end chips
<azonenberg> the LXT are higher end
<azonenberg> he GTP transceiver includes an 8B/10B decoder to decode RX data without consuming
<azonenberg> FPGA resources. The decoder includes status signals to indicate errors and incoming
<azonenberg> control sequences. If decoding is not needed, the block can be disabled to minimize latency.
<lekernel> lattice says it works for receiving too
<azonenberg> Hmm
<azonenberg> Is it possible to do clock recovery on TMDS data?
<azonenberg> LOL
<azonenberg> anyway reading pages 150-160 of UG386 suggests it may be possible to use external clocking on the rx
<azonenberg> not certain yet
<larsc> lekernel: I think I've seen that demo at work today
<larsc> that UI
<larsc> I think a colleague of mine does HDMI RX with a lattice fpga
<Fallenou> :)
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<lekernel> larsc: at what speed?
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<roh> lekernel: bootlab exists. but its only a few persons now
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