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<
kristianpaul>
azonenberg: Hi
<
kristianpaul>
azonenberg: Why you wrote your own uart core for the red tin logic analizer and no re-used one from somewhere else?
<
Hodapp>
azonenberg hangs out here?
<
larsc>
all the cool kids do, don't they? ;)
<
azonenberg>
kristianpaul: i wanted something simple that had a raw interface
<
azonenberg>
rather than forcing use of wishbone or some other bus
<
azonenberg>
like the opencores one did
<
azonenberg>
i had written the uart a while ago for a different project anyway
<
azonenberg>
so just dropped it in
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<
kristianpaul>
have you tried faster speeds than the 115kpbs?
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