<lekernel>
I haven't written a proper academic paper yet I'm afraid...
<azonenberg>
lekernel: ok
<azonenberg>
I'm doing some work on NoC for my thesis and am thinking of exploring methods of automatically generating optimal topologies from activity traces
<lekernel>
there isn't much in-circuit debug, just some debug cores that can be mapped to the CPU bus
<azonenberg>
so i'm looking for prior examples of programmatically generating bus/NoC topology
<azonenberg>
And I see, i'm trying to get something a little more involved
<azonenberg>
Do you guys do hardware cosimulation at all?
<lekernel>
not yet
<azonenberg>
You guys would love the stuff i'm developing then
<azonenberg>
i need another month or so to get it to the point that it's usable
<azonenberg>
And i'm not sure how hard it would be to port it to wishbone since a few of the modules have hard-coded my NoC frame structure
<azonenberg>
But basically I make a VPN into the NoC from my PC
<azonenberg>
and then am able to send NoC frames to any core on the chip over TCP sockets
<azonenberg>
From any application on my laptop including but not limited to a bridge that talks to ISim
<azonenberg>
i have a verilog core that pretends to be a NoC router and sends frames to the nocswitch binary which then forwards over jtag to the board
<azonenberg>
all of the routing just works because of the hierarchal address space, the simulated stuff just shows up as another block of address space
<azonenberg>
And since the NoC is multimaster i can then send traffic to any core on the bus from it
<azonenberg>
So I could code up a quick testbench, run it in the simulator, have it send messages to real hardware, and print everything that goes between them
<lekernel>
azonenberg, btw, any luck with coaxing ACM into putting your paper into the public domain?
<azonenberg>
I haven't submitted anything yet
<azonenberg>
I'm putting most of my effort now into a survey paper
<azonenberg>
Both because it's my research qualifying exam, and because it will give me a better idea of prior work related to what i'm doing
<lekernel>
they're pestering me with unfriendly copyright forms and email requests atm, and I'm wondering what is the most efficient way to deal with those
<azonenberg>
oh joy
<azonenberg>
Submit to another journal instead? :P
<azonenberg>
also, yay - my issue tracker has <50 tickets on it for the first time in a week :D
<azonenberg>
open, that is
<wpwrak>
lekernel: at EPFL, we made a technical report from each paper we submitted to a conference/journal. the TR had different formatting and usually contained a bit more material. the TRs were openly available. nobody ever complained :)
<azonenberg>
sneaky
<azonenberg>
So you let them claim the rights to the paper and then you publish the TR
<azonenberg>
make the TR slightly more in-depth
<lekernel>
I have selected "I'm a US govt employee" in their automatic system so that their sneaky javascript-based form made the "public domain" checkbox appear, unfortunately, someone noticed
<wpwrak>
oh, the TR usually went out first. papers can take forever before they appear.
<azonenberg>
and the journal can hardly complain about you releasing your future work
<azonenberg>
what i mean is, by making the TR look like it came after the paper
<azonenberg>
the journal can't complain about you publishing work you did "after" the paper that happens to include some of the old material
<lekernel>
wpwrak, they have the "no more need to publish it" answer for those cases, so be careful
<lekernel>
"I replied to ACM legal explaining that I have put a copy of my publication on the arXiv under a public domain dedication and therefore I was unable to transfer copyright to them. ACM legal replied, I understand that you have placed your paper in the public domain and on the arXiv site. It is therefore considered as published and there is no need for ACM to republish it in the WGP proceedings."
<wpwrak>
azonenberg: naw, no need to go extremes trying to hide things. there's not much of a conflict anyway. the IEEE/Springer/Elsevier/etc. publications have their role for scoring anyway. it's only now that this is changing
<wpwrak>
lekernel: well, it's not the SAME paper ;-)
<azonenberg>
yeah, that's the tricky part
<azonenberg>
not being the same thing
<wpwrak>
that's easy. starts with the formatting (which tends to require small content adaptations, too). and you often have size limits on journal/conference papers, so you end up trimming it anyway.
<azonenberg>
Yeah, adding new content is to me the biggest thing that makes the TR different
<wpwrak>
and you make have stuff like measurements that you'd never put into a journal but that doesn't get in the way if you put it into a TR
<wpwrak>
s/make/may/
<azonenberg>
yep
<wpwrak>
so unless the publisher is actively looking for a fight, there's enough plausible deniability to avoid conflict
<azonenberg>
Yeah
<azonenberg>
The big thing is, it would be seen as unreasonable for them to prohibit you from publishing a TR based on work you did after the journal paper was submitted
<azonenberg>
and it's expected that you'd include your earlier work for background
<lekernel>
is there anyone who sees their current download fees as reasonable?
<azonenberg>
legally it's still a copyright gray area, especially if you re-use figures etc
<azonenberg>
I have free access through my school but the numbers i see are absurd
<wpwrak>
work done later, definitely. but i think the same goes for any work that's not in the paper, also if done before.
<azonenberg>
$20+ for one paper
<azonenberg>
Yeah
<lekernel>
yeah and your school library is paying through the nose for the subscriptions
<azonenberg>
lekernel: oh, i believe it
<azonenberg>
So far my only cited paper has never been published in such a journal
<azonenberg>
i just posted it on my own website and people found it
<wpwrak>
heh, my most successful paper, according to citeseer: "Linux Network Traffic Control - Implementation Overview (1999)"
<wpwrak>
and people say academics have no sense for the practical :)
<azonenberg>
lol
<azonenberg>
i am a very applied person too
<azonenberg>
But I like to do pure applications and not waste time with such frivolities as how to make money with it
<azonenberg>
which most companies sadly seem to put as their first priority
<azonenberg>
the world needs more nonprofit R&D labs
<wpwrak>
indeed !
<azonenberg>
My first priority is "solve $PROBLEM as well as i possibly can"
<azonenberg>
not "solve $PROBLEM well enough to meet the needs of 70-80% of our potential customer base, at the minimum cost, while doing just enough work that they don't demand refunds"
<wpwrak>
we should be compensated for the damage we're not doing. after all, bright fellows like us could also have gone into finance and cooked up some novel ruinous bubble-production schemes
<azonenberg>
Or built a nuclear device :P
<azonenberg>
If all of the bored engineers in the world got together we could probably build a small nuke in a few years' time
<wpwrak>
breed black holes at CERN
<azonenberg>
lol
<wpwrak>
"a few years" ? c'mon
<azonenberg>
i'm actually idly curious about that
<azonenberg>
there are all kinds of nonproliferation treaties restricting what you can export
<azonenberg>
But i suspect if a group within say the USA decided to build a nuke from domestic parts it would be a lot easier :P
<azonenberg>
Back to on-topic stuff
<azonenberg>
i've been noticing an annoying problem with kicad, it always puts a pad around a via on every layer
<lekernel>
aha, we could have had He-3 at EHSM ;)
<azonenberg>
even if you are not connecting to it
<azonenberg>
Which means if I have a via from top to bottom, an inner layer trace has to stay (annular ring + clearance) away from it
<lekernel>
hopefully we'll have dilution refrigerators and things like that at some future edition
<azonenberg>
lekernel: maybe i can make it to the next one in person
<azonenberg>
how did john's talk go?
<larsc>
In my opinion it was very well done
<lekernel>
I had to take care of the conference cash desk and missed it :(
<azonenberg>
lekernel: :(
<azonenberg>
BTW idk if i mentioned before in here but i was looking at the coolrunner-ii CPLDs
<azonenberg>
as a side project in parallel with fpgatools
<lekernel>
I still need to watch the video ...
<azonenberg>
they're about the cheapest programmable logic around (at least for the small like 32 macrocell units)
<azonenberg>
the bitstreams are tiny
<azonenberg>
And the JED files xilinx tools generate have comments in them :D
<azonenberg>
they partition the fuses into the AND array, the OR array, the interconnect, global clock, etc
<azonenberg>
I feel like once i have time to sit down and play with it i could probably bang out a basic compiler in a few weeks
<azonenberg>
at most
<azonenberg>
wolfgang's work is all well and good for high-capacity stuff but CR-II is something i think we could feasibly have a full FOSS toolchain for pretty quickly
<azonenberg>
libjtaghal can already program spartan-6 and as soon as a board i designed (currently at the fab) with an FT232H and XC2C32A is done i will write a CR-II bitstream loader module for it
<azonenberg>
So we could have a full end-to-end FOSS toolchain for *a* currently shipping programmable logic device
<larsc>
yea!
<azonenberg>
Even if it is just a 32-macrocell CPLD (with eventual scaling to larger devices)
<azonenberg>
i'm debating whether to try writing my own super-simple synthesis tool or try to hack iverilog
<azonenberg>
since it no longer seems to support synthesis
<wpwrak>
a toolchain for CPLDs would be awsome
<azonenberg>
For the first attempt of course i'll be entering manual sum-of-products expressions by hand in some kind of text file
<azonenberg>
wpwrak: well it's actively in progress
<azonenberg>
i'm going bottom up
<azonenberg>
first, load flash images onto the chip (that's waiting on the board)
<azonenberg>
then, take hand-generated product terms and config settings and make a bitstream
<azonenberg>
then synthesize verilog to that intermediate represnetation
<azonenberg>
first target is XC2C32A, then scaling to larger CR-II devices later on
<azonenberg>
the 64a is pin compatible in tqfp 44 so i can put it on the same PCB and test it too
<wpwrak>
the important part is breaking the veil of secrecy
<azonenberg>
there isnt much with the coolrunners
<azonenberg>
the arch seems pretty simple and well documented
<wpwrak>
once you have concept and mapping, people can get to work
<azonenberg>
The bitstream almost doesn't need reversing
<azonenberg>
This is what the xilinx tools generate
<azonenberg>
look at that
<wpwrak>
sounds perfect. a small price tag is always good.
<azonenberg>
"Block 0 PLA AND array" is a comment in the source
<azonenberg>
this is the equivalent of a .bit
<azonenberg>
this is not output from my tools, the compiler generates it
<azonenberg>
And each one of those 1s and 0s is directly written to a flash cell
<wpwrak>
still needs a bit of interpreting :)
<azonenberg>
Sure, but not much
<azonenberg>
The chip starts at $1.20 for the lowest speed grade in single units
<wpwrak>
yeah, could be much worse
<azonenberg>
So it would be a great stepping stone
<azonenberg>
It can't share much code with fpgatools since the microarchitecture is so different, unfortunately
<wpwrak>
though i think the FPGA bitstreams aren't all that different either (at least that's the impression i got from wolfgang's descriptions)
<azonenberg>
FPGA bitstreams you need to start from scratch more since the bit file isnt commented
<azonenberg>
and there are soooo many different types of tile
<wpwrak>
yes, but it's also one bit = one switch or similar
<azonenberg>
the CPLD is basically a PLA and a bit of global routing
<azonenberg>
and nothign else
<azonenberg>
no ram, no multipliers
<wpwrak>
yeah, CPLDs are simpler :)
<azonenberg>
n oserializers
<azonenberg>
Which makes it a very attractive first study target
<larsc>
how much logic could you fit in there?
<azonenberg>
32 macrocells is the smallest CR-II device
<azonenberg>
each macrocell is able to implement a sum-of-products expression with up to i think around 56 inputs
<azonenberg>
or is it 40?
<azonenberg>
i have this written down somewhere
<azonenberg>
and then output both directly and throguh a flipflop
<wpwrak>
so only 32 FFs ?
<azonenberg>
in my experience, once you start doing state machines the limiting factor is running out of FFs
<azonenberg>
Yes
<larsc>
and one macrocell is flipflop + lut?
<azonenberg>
But the CR-II line gets bigger
<azonenberg>
they go up to 512 macrocells
<azonenberg>
larsc: no, they aren't LUT based
<azonenberg>
CPLD microarchitecture is very different
<wpwrak>
getting better :)
<azonenberg>
it's a big and-or array
<azonenberg>
wpwrak: Those are $$$ though
<azonenberg>
256 is like $20
<azonenberg>
384 and 512 are absurd
<azonenberg>
But 32/64/128 are relatively cheap
<azonenberg>
those are my main targets, for glue-logic type applications
<azonenberg>
if you need more than 128 macrocells for your system, go talk to wolfgang :P
<azonenberg>
iirc 256 macrocells is enough to fit a picoblaze CPU
<azonenberg>
or is it 128
<azonenberg>
but it needs external flash for the program rom i think
<wpwrak>
hmm, for USD 20 you already get three XC6LX9 in china
<wpwrak>
or 1.3 at digi-key
<azonenberg>
Yes
<azonenberg>
Its not cost effective to buy big cplds
<azonenberg>
Hence why the small ones are my target
<azonenberg>
xc6slx4/9 start at like $8-10
<azonenberg>
but you can get 32 / 64 / 128 macrocells of CR-II cheaper
<azonenberg>
and in a nice friendly 0.8mm TQFP for the 32/64
<azonenberg>
noob friendly
<wpwrak>
;-)
<wpwrak>
XC2C64A seems to be the largest that's still friendly
<wpwrak>
after that, prices jump and packages get large
<wpwrak>
for making a very cheap board, a Ben interface (using UBB) may be an attractive option: you have GPIOs for JTAG, the Ben can supply 3.3 V, and it can even supply the clock (up to 56 MHz)
<wpwrak>
i don't know if you're reading the qi-hardware list. i already have a proof of concept for JTAG. urtag on the ben talks nicely to the milkymist one :)
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<kristianpaul>
azonenberg: Hi, is your NoC related work going or already been public?
* kristianpaul
want to profit with NoC's at soho level
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<Fallenou>
15:13 < azonenberg> how did john's talk go? < it was really good !
<azonenberg>
kristianpaul: will be made public, yes
<azonenberg>
is, no
<azonenberg>
Step 1, debug infrastructure
<azonenberg>
I will be publishing that as well as a survey paper in the spring some time
<azonenberg>
step 2, build something on top of that
<azonenberg>
Will be published when i finish my thesis
<azonenberg>
there may be other intermediate steps too
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<GitHub152>
lm32/master 68d407f Yann Sionneau: fix compilation of lm32 tests...
<GitHub152>
lm32/master e937900 Yann Sionneau: lm32 test Makefiles cleanup...
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<mwalle>
wpwrak: why do you need fjmem?
<mwalle>
wpwrak: and whats the use of the breakout board actually?
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<wpwrak>
(fjmem) to do through the motions of using urtag on the milkymist. it's just a proof of concept, so i tried to do whatever we do there, to prove that all this works
<wpwrak>
an actual use i have in mind would be for a low-cost fpga/etc. experimentation board
<wpwrak>
basically the hardware for fpgatools, but without all the overhead of ftdi, oscillator, and so on
<wpwrak>
just the fpga, one reg for Vcore, a few LEDs, a few headers, done. nanonote can supply 3.3 V, clock, and jtag