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<
larsc>
sb0: how is cape town?
<
sb0>
sunny, it's 30C here
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<
wpwrak>
adding a bit of vacation after the conference ?
<
sb0>
no, I fly back on the 31st... looking forward to a nice hiking/urbex/bbq weekend though
<
sb0>
tomorrow is another day at the SKA office, and more Migen pitching there - would be nice to get more contribs
<
sb0>
pretty much everyone there hates EDK and Simulink that a Migen-based solution could nicely replace, but they love legacy code...
<
wpwrak>
legacy is always a bit problem. lots and lots of inertia ...
<
sb0>
after I'm back I should have more time to work on M3 and video mixing... now that I no longer have major distractions like EHSM...
<
sb0>
would be nice if Florent gets the DDR3 to work on kintex-7
<
Fallenou>
sb0: have you fixed the bug in migen.fhdl.verilog in convert() that outputs different verilog code when calling several times convert()?
<
Fallenou>
adding sys_clk1 sys_clk2 etc
<
sb0>
haven't looked at it
<
Fallenou>
I did a "private session" (rattrapage) of the migen workshop for Alarm in mp
<
sb0>
it's on my list ...
<
Fallenou>
and we hit that bug as well
<
Fallenou>
hum, it's the call to ios.add()
<
Fallenou>
each time it adds a new io for clk and rst
<
Fallenou>
hum not sure ...
<
sb0>
let me try...
<
GitHub59>
migen/master 3201554 Sebastien Bourdeauducq: fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
<
sb0>
should be fixed now, thanks for the hint
<
sb0>
Fallenou, is the problem gone?
<
Fallenou>
I don't know, I'm at the office right now, I will try at home and I will quickly let you know :)
<
Fallenou>
thanks for the quick commit
<
Fallenou>
sb0: it seems fixed now :)
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