<pepijndevos>
ohhh I'm dumb... I have been running a dev version, nuked my virtualenv due to python upgrade, and ended up with a stable version that's actually older than what I was using.
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<d1b2>
<dub_dub_11> I'm trying to write an audio codec (AC97) controller, and the interface is clocked by the codec In a similar manner to SPI with the FPGA as a slave (sample on posedge of bit_clk, shift on negedge). My question is how do I drive the bit_clk_n domain from bit_clk? I tried m.d.comb += bit_clk_n.clk.eq(bit_clk.clk)but when I simulated I got three nets, bit_clk_clk, bit_clk_clk$1 which was always zero and bit_clk_n_clk which was also always zero
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<vup>
@dub_dub_11 did you `sim.add_clock` the `bit_clk`?
<d1b2>
<dub_dub_11> Yeah
<d1b2>
<dub_dub_11> bit_clk_clk was the right clock signal at the right frequency
<d1b2>
<dub_dub_11> But bit_clk_n_clk wasn't getting driven by it
<vup>
ah I missunderstood your original sentence
<agg>
dub_dub_11: I think you'll need to add every clock to the simulator individually, it essentially can't have logic 'generate' clocks which then drive other synchronous logic
<agg>
(in your actual module you'll need to add a clock domain for each clock, too, if you're not already)
<d1b2>
<dub_dub_11> Ok
<d1b2>
<dub_dub_11> That works for simulator, I'm not sure how it will end up looking when I go to synthesise though
<agg>
in synthesis it's possible to drive clock domains from whatever signal using m.d.comb += clock_domain.clk.eq(bla) as you've done, but...
<agg>
you might instead use your fpga's ddr io logic
<agg>
so the i/o cell captures on the rising and falling edge of a specific clock, and presents your gateware with the two signals together
<d1b2>
<dub_dub_11> Yeah DDR might make more sense in the end, just duplicating/throwing away half the bits
<agg>
often that's easier than trying to do multiple clock domain logic
<agg>
not like they're wasted or anything
<d1b2>
<dub_dub_11> Yeah true
<agg>
that said, vup's example does work fine, so I must have been thinking of some older behaviour of the simulator
<d1b2>
<dub_dub_11> Ah. I will consider both. That example looks a lot like my code so I will check the difference
<d1b2>
<dub_dub_11> And there would need to be a frame sync signal passed between domains so DDR is probably cleaner
<agg>
DDR also helps guarantee the relative timing is right and the capture happens right at the I/O cell, rather than some routing-dependent time after the signal enters your logic
<d1b2>
<dub_dub_11> Yeah that makes sense
<d1b2>
<dub_dub_11> I would also imagine that I should make the bit_clk input in the board file a clocking Resource so it can do timing analysis
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<whitequark>
agg: you *can* have logic generate clocks in the simulator
<whitequark>
it's explicitly supported in pysim
<agg>
whitequark: was that always the case? I'm sure I tried it ages ago and had issues but obviously it works fine now
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<whitequark>
agg: it wasn't the case on migen
<d1b2>
<dub_dub_11> ahh
<d1b2>
<dub_dub_11> the run_passive=True fixed it
<d1b2>
<dub_dub_11> I will still consider using ddr though
<d1b2>
<dub_dub_11> for the reasons you mentioned
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<_whitenotifier-4>
[nmigen] RobertBaruch opened issue #555: Any way to warn about & in if? - https://git.io/JInBk
<_whitenotifier-4>
[nmigen] whitequark commented on issue #555: Any way to warn about & in if? - https://git.io/JInBm
<_whitenotifier-4>
[nmigen] RobertBaruch commented on issue #555: Any way to warn about & in if? - https://git.io/JInBO
<_whitenotifier-4>
[nmigen] RobertBaruch closed issue #555: Any way to warn about & in if? - https://git.io/JInBk
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<_whitenotifier-4>
[nmigen] RobertBaruch commented on issue #380: Emit a diagnostic when parentheses are omitted in logical expressions with comparisons - https://git.io/JInBM
<_whitenotifier-4>
[nmigen] whitequark commented on issue #380: Emit a diagnostic when parentheses are omitted in logical expressions with comparisons - https://git.io/JInBd
<_whitenotifier-4>
[nmigen] whitequark edited a comment on issue #380: Emit a diagnostic when parentheses are omitted in logical expressions with comparisons - https://git.io/JInBd
<lkcl>
FOSDEM 2021 CFP is up, and my feeling is that it's going to be *big* this year, entirely online.
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<lkcl>
with talks being submitted as pre-recorded video i'd love to see a nmigen talk
<whitequark>
i barely have enough time to do all the work that needs to be done, much less prepare a talk
<_whitenotifier-4>
[nmigen] RobertBaruch commented on issue #380: Emit a diagnostic when parentheses are omitted in logical expressions with comparisons - https://git.io/JInRb
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<_whitenotifier-4>
[nmigen] RobertBaruch commented on issue #380: Emit a diagnostic when parentheses are omitted in logical expressions with comparisons - https://git.io/JIn0k
<_whitenotifier-4>
[nmigen] whitequark commented on issue #380: Emit a diagnostic when parentheses are omitted in logical expressions with comparisons - https://git.io/JIn0G
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<_whitenotifier-4>
[nmigen] RobertBaruch commented on issue #380: Emit a diagnostic when parentheses are omitted in logical expressions with comparisons - https://git.io/JInEk
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<_whitenotifier-4>
[nmigen] whitequark commented on issue #380: Emit a diagnostic when parentheses are omitted in logical expressions with comparisons - https://git.io/JInEV
<_whitenotifier-4>
[nmigen] whitequark deleted a comment on issue #380: Emit a diagnostic when parentheses are omitted in logical expressions with comparisons - https://git.io/JInEV
<_whitenotifier-4>
[nmigen] whitequark commented on issue #380: Emit a diagnostic when parentheses are omitted in logical expressions with comparisons - https://git.io/JInEi
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<lkcl>
whitequark: ok. i have been mentioning it in libresoc talks, that nmigen is extremely powerful and flexible. i'll make sure to provide links and may go a bit more in-depth (because it's FOSDEM)
<whitequark>
okay
<lkcl>
you created something that's ****** awesome, whitequark: people deserve to know :)