ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at · IRC meetings each Monday at 1800 UTC · next meeting TBD
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<_whitenotifier> [nmigen] RobertBaruch commented on issue #562: Way to start register with "random" value? -
<_whitenotifier> [nmigen] whitequark commented on issue #562: Way to start register with "random" value? -
<_whitenotifier> [nmigen] RobertBaruch commented on issue #562: Way to start register with "random" value? -
<_whitenotifier> [nmigen] whitequark commented on issue #562: Way to start register with "random" value? -
<_whitenotifier> [nmigen] RobertBaruch commented on issue #562: Way to start register with "random" value? -
<_whitenotifier> [nmigen] RobertBaruch edited a comment on issue #562: Way to start register with "random" value? -
<_whitenotifier> [nmigen] RobertBaruch edited a comment on issue #562: Way to start register with "random" value? -
<_whitenotifier> [nmigen] RobertBaruch edited a comment on issue #562: Way to start register with "random" value? -
<_whitenotifier> [nmigen] RobertBaruch edited a comment on issue #562: Way to start register with "random" value? -
<_whitenotifier> [nmigen] RobertBaruch edited a comment on issue #562: Way to start register with "random" value? -
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<mithro> Anyone here looked at before?
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<nono2357[m]> <mithro "Anyone here looked at https://he"> nice pick!
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<mwk> hrm, seems hammering in Versal support is non-trivial
<mwk> stuck on the bitstream generation stage
<mwk> or rather, device image generation stage, because bitstreams are supposedly no longer a thing
<JJJollyjim> why would there be bitstreams when it isn't an fpga? /s
<JJJollyjim> it's a checks notes acab?
<mwk> yea, it's an acap, and most definitely not a glorified Zynq
<mwk> *sigh* so once I can get the DRC to pass I'm going to obtain, what, an ELF file with a bitstream embedded in it?
<daveshah> Its a PDI, its several layers of encapsulation with elf files and a bitstream inside that
<daveshah> elf files both for the microblaze control stuff and the ARMs
<daveshah> you can kinda figure out how it fits together if you stare at the various structures in
<mwk> fantastic
<mwk> any idea how to get the "no CIPS IP" DRC error to fuck off without actually, y'know, instantiating the damned IP?
<daveshah> set_property SEVERITY Warning [get_drc_checks]#
<daveshah> there's doubtless a less blunt hammer though
<daveshah> (you can just disable the CIPS check but I don't have the number for that around)
<mwk> yea, I mean, how to shut up that thing properly
<daveshah> idk, maybe a PS9 primitive would do it
<mwk> for Zynq, you instantiate PS7/PS8 and you're good to go
<mwk> nah, tried it
<daveshah> no idea then
<daveshah> I wouldn't be surprised if you did have to have a fucking CIPS IP core
<mwk> me neither
<daveshah> around the time of the versal launch a professor heard a rumour that Xilinx wouldn't support Verilog flows at all
<daveshah> it does seem like you might have to at a minimum use their IP stuff
<mwk> ... well I'm not using a Verilog flow
<daveshah> looking at the cips IP xdc it has another command
<daveshah> set_property HD.TANDEM_BITSTREAMS COMBINED [current_design]
<daveshah> (as well as set_property DONT_TOUCH true [get_cells PS9_inst] )
<d1b2> <ronyrus> hi, I'm playing with implementing a simple SPI peripheral in nMigen. I use an FTDI chip as the SPI controller. SPI clock is 30 MHz and the 'sync' in the FPGA is 120 MHz. I'm getting weird behavior unless I'm FFSyncing the signals coming from outside. I thought CDC is applicable only when there are two actual clocks present, but I'm treating SPI clk as a signal not a clock. Is it a debouncing issue? Do I need it only on input signals? Also, what happens
<d1b2> if SPI clk and the sync clk are closer than in my case? FFSynchronizer adds 2 clock latency. How should it be solved then? Sorry about noob questions. Feel free to send me read some resource (don't forget to give a link though :-P).
<mwk> ronyrus: yeah you have to use FFSynchronizer, unless you're really sure that the incoming data is actually synchronous to the clock
<daveshah> ah, looks like it also generates a hwdef file containing some json and cdo config files that are probably the magic things it complains about
<mwk> for SPI you may get away with using the SPI clock as, well, an actual clock, but be careful about the rules for sampling the input and changing output on the right clock edges
<daveshah> and the all-important microblaze elf
<mwk> ... right, it did complain about not having a hardware definition file, whatever that is
<mwk> I'm going to try disabling the DRC checks and see what happens
<mwk> ... will I get a boneless device image in that case
<daveshah> who knows
<mwk> elves have bones, right?
<daveshah> lol
<d1b2> <ronyrus> so, using SPI clk as a clock trades latency on the clock for latency on the data? I would still have to cross the clock domains.
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<daveshah> hmm, power_data.json in the PDI is interesting - XML with Tcl strings inside a Verilog attribute inside JSON
<daveshah> "pss_power": "(*PSS_POWER= \"<BLOCKTYPE name={PS9}> <PS><BPD Power_Gate={Enable} RTC_Power_Gate={Enable}></BPD><FPD><PROCESSSORS><PROCESSOR name={Cortex A-72} numCores={2} L2Cache={Enable} clockFreq={1350.000000} ...
<JJJollyjim> D:
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<daveshah> *in the hwdef, not pdi
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<daveshah> it's OK, you can have CSV instead if you don't like XML
<daveshah> "pss_io": "(*PSS_IO= \"Signal Name, DiffPair Type, DiffPair Signal,Direction, Site Type, IO Standard, Drive (mA), Slew Rate, Pull Type, IBIS Model, ODT, OUTPUT_IMPEDANCE \\n\\\nQSPI_X4_QSPI0_CLK,
<daveshah> or recursive JSON if you still aren't happy
<daveshah> "SATELLITE_SYSMON_0" : "{ \"belname\": \"SYSMON_SAT_X16Y11/SYSMON_SAT\", \"attrVals\": [ {\"attr\":\"TOKEN_MNGR\", \"val\": \"0x000000FF\"}, {\"attr\":\"ADC_CTRL0\", \"val\": \"0x001F1D77\"}, {\"attr\":\"ADC_CTRL1\", \"val\": \"0x0000000F\"},
<mwk> this.... this is the file that it expects so that it will make a definitely-not-bitstream for me?
<mwk> I'm actually supposed to WRITE THIS PIECE OF SHIT?
<daveshah> these are in it, anyway
<daveshah> no, you are supposed to use the wizard and question nothing
<daveshah> this isn't even a zip file, it's an hwdef file that you definitely aren't supposed to open
<daveshah> these lines in the cdo files (startup register write commands) really inspire confidence
<daveshah> # DEFUNCT-No longer used. Reset for Individual block
<daveshah> mask_write 0xfd1a0310 0x1 0
<mwk> heh.
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<mwk> "Creating bitstream..." encouraging
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<mwk> well it created... something
<mwk> hm, got .rnpi file and .rcdo file
<daveshah> Those are really just text intermediate files, afaik
<mwk> they're the only build artifacts I can see
<daveshah> No pdi file?
<daveshah> That's what the final device image should end with
<mwk> ohhh
<mwk> right
<daveshah> It might not generate that until it has the hwdef-of-cursed-json
<mwk> nah, there is a file, I just didn't notice it
<daveshah> (sorry, I misspoke earlier when I said the cursed-json was in the pdi, mixed up the various encapsulations)
<daveshah> OK good, ship it then
<daveshah> Knowing fpga launches it'll be a while before anyone has any actual hardware to test it on and complain anyway
<mwk> ... true
<mwk> this doesn't look like older bitstreams
<mwk> at any place
<mwk> ah well
<daveshah> If you disable compression, one of the files contains something that structurally isn't far away from an old bitstream but 128 bit aligned
<daveshah> The command format looks a bit different too
<mwk> hm, alright
<mwk> I suppose it's not the time to look at it yet
<daveshah> I had a brief look because shiny but yeah
<daveshah> if these prices on octopart are right, I won't be getting one any time soon even when they are released >>
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<mwk> ... right
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<mwk> huh, interesting
<mwk> seems there really isn't a bitstream
<mwk> as in, instead of having a configuration controller that slurps a bitstream and pokes internal regs according to the commands, the internal regs are instead directly visible on the internal AXI/whatever bus
<mwk> and the pdi file is really a list of addresses and data to poke into them
<mwk> that would explain the lack of familiar framing
<daveshah> inside the main bitstream cdo file there is a big 'write keyhole DMA' command that contains the whole 'bitstream' as a payload
<daveshah> bootgen can unpack the pdi files and cdoutil the cdo files inside that
<daveshah> Xilinx really liked container formats, it seems
<mwk> apparently
<Sarayan> I heard you liked containers so we put a container in your container
<mwk> ... how many microblazes are in this thing anyway
<JJJollyjim> don't say container too loud or they'll overhear and package it into a docker container next
<daveshah> I think there are microblazes in the DDR controllers and transceivers too
<daveshah> and does a TMR microblaze count as 1 or 3
<mwk> "there are low-latency datapaths, high throughput datapaths, and noteworthy datapaths"
<mwk> the three genders
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<lkcl> Sarayan: try to contain yourself, please...
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<cr1901_modern> daveshah: TMR? The thing you do to cats?
<daveshah> triple modular redundancy
<cr1901_modern> ahhh
<daveshah> they started using TMR MicroBlazes for control in the Zynq UltraScale+
<mwk> and are now apparently just spraying them
<mwk> I still cannot figure out why PPU and PSM are two different things
<daveshah> because the engineers had a competition as to how many microblazes they could cram in?
<awygle> .... what do you do to cats?
<cr1901_modern> T*N*R
<awygle> anyway i'll bet money they hired a new lead/principal/manager/vp and they had to change something to justify their salary
<awygle> i had never heard of that acronym before
<awygle> TIL
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<JJJollyjim> are they hard microblazes? or does the software synthesize soft ones for all these places?