<daveshah>
(as well as set_property DONT_TOUCH true [get_cells PS9_inst] )
<d1b2>
<ronyrus> hi, I'm playing with implementing a simple SPI peripheral in nMigen. I use an FTDI chip as the SPI controller. SPI clock is 30 MHz and the 'sync' in the FPGA is 120 MHz. I'm getting weird behavior unless I'm FFSyncing the signals coming from outside. I thought CDC is applicable only when there are two actual clocks present, but I'm treating SPI clk as a signal not a clock. Is it a debouncing issue? Do I need it only on input signals? Also, what happens
<d1b2>
if SPI clk and the sync clk are closer than in my case? FFSynchronizer adds 2 clock latency. How should it be solved then? Sorry about noob questions. Feel free to send me read some resource (don't forget to give a link though :-P).
<mwk>
ronyrus: yeah you have to use FFSynchronizer, unless you're really sure that the incoming data is actually synchronous to the clock
<daveshah>
ah, looks like it also generates a hwdef file containing some json and cdo config files that are probably the magic things it complains about
<mwk>
for SPI you may get away with using the SPI clock as, well, an actual clock, but be careful about the rules for sampling the input and changing output on the right clock edges
<daveshah>
and the all-important microblaze elf
<mwk>
... right, it did complain about not having a hardware definition file, whatever that is
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<mwk>
huh, interesting
<mwk>
seems there really isn't a bitstream
<mwk>
as in, instead of having a configuration controller that slurps a bitstream and pokes internal regs according to the commands, the internal regs are instead directly visible on the internal AXI/whatever bus
<mwk>
and the pdi file is really a list of addresses and data to poke into them
<mwk>
that would explain the lack of familiar framing
<daveshah>
inside the main bitstream cdo file there is a big 'write keyhole DMA' command that contains the whole 'bitstream' as a payload
<daveshah>
bootgen can unpack the pdi files and cdoutil the cdo files inside that
<daveshah>
Xilinx really liked container formats, it seems
<mwk>
apparently
<Sarayan>
I heard you liked containers so we put a container in your container
<mwk>
... how many microblazes are in this thing anyway
<JJJollyjim>
don't say container too loud or they'll overhear and package it into a docker container next
<daveshah>
I think there are microblazes in the DDR controllers and transceivers too
<daveshah>
and does a TMR microblaze count as 1 or 3
<mwk>
"there are low-latency datapaths, high throughput datapaths, and noteworthy datapaths"
<mwk>
the three genders
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<lkcl>
Sarayan: try to contain yourself, please...
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<cr1901_modern>
daveshah: TMR? The thing you do to cats?
<daveshah>
triple modular redundancy
<cr1901_modern>
ahhh
<daveshah>
they started using TMR MicroBlazes for control in the Zynq UltraScale+
<mwk>
and are now apparently just spraying them
<mwk>
I still cannot figure out why PPU and PSM are two different things
<daveshah>
because the engineers had a competition as to how many microblazes they could cram in?
<awygle>
.... what do you do to cats?
<cr1901_modern>
T*N*R
<awygle>
anyway i'll bet money they hired a new lead/principal/manager/vp and they had to change something to justify their salary
<awygle>
i had never heard of that acronym before
<awygle>
TIL
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<JJJollyjim>
are they hard microblazes? or does the software synthesize soft ones for all these places?