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<awygle>
whitequark: the eval_comb eval_sync thing is what i was going to suggest
<awygle>
or really, float as an idea
<awygle>
i was going to call them something like "settle" and "register" but those names ar eprobably worse
Bertl_zZ is now known as Bertl
<_whitenotifier>
[nmigen] cestrauss opened issue #561: cxxsim: testbench-only signals are placed at root level on the VCD file - https://git.io/JI5LR
<_whitenotifier>
[nmigen] whitequark commented on issue #561: cxxsim: testbench-only signals are placed at root level on the VCD file - https://git.io/JI5mS
<_whitenotifier>
[nmigen] cestrauss commented on issue #561: cxxsim: testbench-only signals are placed at root level on the VCD file - https://git.io/JI5ab
<_whitenotifier>
[nmigen] cestrauss edited issue #561: pysim: testbench-only signals are not placed at root level on the VCD file - https://git.io/JI5LR
<_whitenotifier>
[nmigen] cestrauss edited a comment on issue #561: pysim: testbench-only signals are not placed at root level on the VCD file - https://git.io/JI5ab